On Mon, Nov 02, 2026 at 03:17:25PM +0100, marouene.boubakri@oss.nxp.com wrote:
> From: Marouene Boubakri <marouene.boubakri@oss.nxp.com>
> 
> Add the SoC selection entry for OpenHW Group platforms, which is used
> to build the device trees of the CVA6 APU FPGA platform.
> 
> Signed-off-by: Marouene Boubakri <marouene.boubakri@oss.nxp.com>
> ---
>  arch/riscv/Kconfig.socs | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index cecbce0c49..289448e489 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -26,6 +26,15 @@ config ARCH_MICROCHIP
>  	help
>  	  This enables support for Microchip SoC platforms.
>  
> +config ARCH_OPENHWGROUP
> +	bool "OpenHW Group SoCs"
> +	help
> +	  This enables support for OpenHW Group SoC platform hardware.

> +	  Current support is for the CVA6 APU, the FPGA platform built
> +	  around the CVA6 application class core, with the 32-bit (cv32a6)
> +	  and 64-bit (cv64a6) configurations of the core on the Digilent
> +	  Genesys 2 board.

Delete all this, it'll just bitrot over time.

> +
>  config ARCH_RENESAS
>  	bool "Renesas RISC-V SoCs"
>  	help
> -- 
> 2.43.0
>