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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4a921353dcfsm7809249fac.0.2026.11.02.11.55.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2026 11:55:24 -0800 (PST) From: James Hilliard Subject: [PATCH v6 0/8] serial: 8250_dw: describe the Allwinner H616 and A523 UART configurations Date: Mon, 02 Nov 2026 12:55:15 -0700 Message-Id: <20261102-submit-h616-uart-fifo-v1-v6-0-25afcb346b0c@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIAAAAAAAC/43SX0/CMBAA8K9C9mxN/3cQY/wehodrd4UaxrQdE 0P47t4A4yRKTPpyafu7Xu8OVcGcsFSL2aHKOKSSui0F9m5WhTVsV8hSQ3ElubSCS8nKzrepZ2s rLNtB7llMsWODYMFADE1EEzyv6Pprxpj2J/p5eY7p7guGfvTGE+tU+i5/nHIPYjz3lUb9nYYWZ 6hBeUCJHuqnVQtpcx+6thrTDPK/kCQIIjdzZbi2ylxDagrpG5AiSNY2BuHroIK4hvQUcjcgTVC jHHJRx4aDvYbMFJrfgAxBRnmtFKD38ccfHc+9yPi2o2735wZVHgoy2ieQuu+1N1pFELUzTs4dB Gcs2IgWrY6GW+9qrWFsYoulwGlMFrOH6xrH4YINq6Whwt5Zk2jAunypVTAtnNDgDAoD3098/Iv Vv7F53+e0YpsUsU8tXkZEMKcEPbIxnKtmai+Px09sO8Gv9QIAAA== X-Change-ID: 20261022-submit-h616-uart-fifo-v1-c5afcdfe5cb0 To: Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, James Hilliard , Krzysztof Kozlowski X-Mailer: b4 0.15.2 Allwinner UARTs use FIFO-relative receive thresholds and an optional register layout that differs from the generic DesignWare integration. Describe the H616 and A523 integrations through dedicated compatibles and common sunxi setup helpers. H616 has fixed 256-byte FIFOs without a readable FIFO-depth register. A523, A527 and T527 have different depths across their UARTs and report each port's depth in the FIFO Clock Control register. Use a fixed platform-data depth when provided, otherwise read FCC in the sunxi setup callback. Derive the transmit load and receive-trigger table from that depth. This keeps one implementation of the common 1-byte, quarter-full, half-full and depth-minus-two mapping for both fixed-depth and runtime-discovered ports. Keep PORT_16550A, configure automatic flow control, preserve BUSY-safe integer divisor programming and keep the UART clock gate enabled during termios changes. The sunxi setup uses PIO. The series first introduces platform setup callbacks and a shared RX trigger conversion helper, then adds the binding, driver and SoC DTS changes for each integration. Based on tty-next at 6b4b543fa187 with the posted RX trigger callback-lifetime fix [0] and DW BUSY-safe divisor fix v4 [1]. Platform setup runs before installing the BUSY-safe divisor setter. [0] https://lore.kernel.org/r/20261024-submit-serial-8250-rxtrig-lifetime-v1-v1-1-731b78d5003d@gmail.com [1] https://lore.kernel.org/r/20261027-submit-serial-8250-dw-divisor-v1-v4-1-41714a75e15a@gmail.com Assisted-by: Codex:gpt-6-astra Signed-off-by: James Hilliard --- Changes in v6: - Export the shared RX trigger conversion in the SERIAL_8250 namespace and explain how driver callbacks avoid new legacy port types. - Lead the H616 trigger description with the FIFO-relative mapping and include array_size.h explicitly. - Name the trigger divisors and full-FIFO margin, reusing them for FCC depth validation. Explain that the upper bound follows the current byte-sized 8250 interface and can be widened with it. - Describe the fixed-depth platform-data field independently of sunxi. - Carry Ilpo's setup/helper review tags and Krzysztof's A523 binding ack. - Link to v5: https://patch.msgid.link/20261029-submit-h616-uart-fifo-v1-v5-0-53b433aebbf8@gmail.com Changes in v5: - Reject FIFO depths that cannot produce positive, byte-sized RX trigger thresholds, report the invalid size and propagate setup errors to probe. - Add the A523 UART compatible and use it for the shared CPUX UART nodes, including those inherited by the A527 and T527 boards. - Read the FIFO depth from FCC when sunxi platform data has no fixed depth, preserving the fixed H616 configuration and FCC clock controls. - Explain why the per-port trigger table is derived from the FIFO depth; use the same sunxi helper for the FCC-discovered A523-family ports. - Move the shared RX trigger conversion helper into 8250_port.c and export it, following Ilpo's review; retain Andy's review tags. - Use FIELD_PREP() and an intermediate trigger value when building the sunxi table, following Ilpo's review. - Select the DMA setup helper directly for the 64-bit-only Octeon platform and match the single-line comment style, following Andy's review. - Carry Krzysztof's Acked-by for the unchanged H616 binding addition. - Link to v4: https://patch.msgid.link/20261027-submit-h616-uart-fifo-v1-v4-0-d37e018fd0a6@gmail.com Changes in v4: - Introduce common Allwinner setup helpers with the fixed FIFO depth supplied by compatible-specific platform data. - Rebase onto tty-next at 6b4b543fa187 and the posted DW divisor v4 fix, installing the BUSY-safe setter after platform setup. - Use an early return for FIFO-less DMA setup, following Andy's review. - Default to generic setup when platform data has no setup callback. - Select Octeon's optional-register discovery with IS_ENABLED() in its setup helper, preserving the existing 32-bit and 64-bit behavior. - Extract the shared 8250 bytes-to-FCR conversion, including the unsupported-table check, into a preparatory patch and use it for H616, following Andy's review. - Set the fixed 256-byte FIFO depth in H616 platform data and omit fifo-size from its binding and DTS, following Krzysztof's review. - Precompute the Allwinner RX thresholds during setup and retain the sunxi FIFO-depth helper for filling the table. Use named FCR encodings in the helper, following Jiri's review. - Share threshold-table initialization and callback assignment through a sunxi RX trigger setup helper. - Group and comment the H616 trigger and RS485 setup. - Link to v3: https://patch.msgid.link/20261024-submit-h616-uart-fifo-v1-v3-0-286fc1b8c3c1@gmail.com Changes in v3: - Introduce a platform-data setup callback in a preparatory patch, replacing skip_autocfg and preserving the existing Octeon setup. - Describe each H616 UART's FIFO capacity with the standard fifo-size DT property and use the value already read by uart_read_port_properties(). - Derive the Allwinner RX trigger thresholds from the FIFO depth. - Use an unsigned trigger index and conditional runtime PM guard, preserving error propagation when the device cannot resume. - Rebase onto tty-next, replacing the earlier DMA prerequisites with the posted RX trigger callback-lifetime fix. - Separate DMA enablement into follow-up work, retaining PIO operation for the H616 FIFO configuration. - Link to v2: https://lore.kernel.org/r/20261023-submit-h616-uart-fifo-v1-v2-0-af0593504635@gmail.com Changes in v2: - Keep PORT_16550A and set the FIFO size, transmit load and capabilities during setup, following Andy's review. - Select H616 setup through the matched platform-data pointer and remove the type and DMA burst-size platform-data members. - Use get_rxtrig/set_rxtrig for the 1/64/128/254-byte receive thresholds, with port locking and runtime PM around register updates. Keep the standard half-full FCR default, selecting 128 bytes on H616. - Advertise UART_CAP_AFE so CRTSCTS enables hardware automatic flow control. - Rebase onto next-20261023 and declare the posted sun6i pause/lifetime fixes and their prerequisites for DMA enablement. - Link to v1: https://lore.kernel.org/r/20261023-submit-h616-uart-fifo-v1-v1-0-e4a3bae2eba8@gmail.com To: Andy Shevchenko To: Ilpo Järvinen To: Greg Kroah-Hartman To: Jiri Slaby To: Rob Herring To: Krzysztof Kozlowski To: Conor Dooley To: Chen-Yu Tsai To: Jernej Skrabec To: Samuel Holland Cc: linux-kernel@vger.kernel.org Cc: linux-serial@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-sunxi@lists.linux.dev --- James Hilliard (8): serial: 8250_dw: select port setup through platform data serial: 8250: share the RX trigger conversion helper dt-bindings: serial: snps-dw-apb-uart: add Allwinner H616 serial: 8250_dw: configure the Allwinner H616 UART arm64: dts: allwinner: h616: describe the UART integration dt-bindings: serial: snps-dw-apb-uart: add Allwinner A523 serial: 8250_dw: discover Allwinner A523 FIFO depths through FCC arm64: dts: allwinner: a523: describe the UART integration .../bindings/serial/snps-dw-apb-uart.yaml | 2 + arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 12 +- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 16 +- drivers/tty/serial/8250/8250.h | 2 + drivers/tty/serial/8250/8250_dw.c | 172 +++++++++++++++++++-- drivers/tty/serial/8250/8250_port.c | 21 ++- 6 files changed, 192 insertions(+), 33 deletions(-) --- base-commit: 6b4b543fa18757297ac756a6fe6e64f506b7844a change-id: 20261022-submit-h616-uart-fifo-v1-c5afcdfe5cb0 prerequisite-message-id: <20261027-submit-serial-8250-dw-divisor-v1-v4-1-41714a75e15a@gmail.com> prerequisite-patch-id: d8219673210dac82d3adab41578ff2f76f5862c9 prerequisite-message-id: <20261024-submit-serial-8250-rxtrig-lifetime-v1-v1-1-731b78d5003d@gmail.com> prerequisite-patch-id: 9a9395c715c2bf7bbcae5bdd16a339d7f2af6269 Best regards, -- James Hilliard