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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4a921353dcfsm7809249fac.0.2026.11.02.11.55.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2026 11:55:32 -0800 (PST) From: James Hilliard Date: Mon, 02 Nov 2026 12:55:22 -0700 Subject: [PATCH v6 7/8] serial: 8250_dw: discover Allwinner A523 FIFO depths through FCC X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261102-submit-h616-uart-fifo-v1-v6-7-25afcb346b0c@gmail.com> References: <20261102-submit-h616-uart-fifo-v1-v6-0-25afcb346b0c@gmail.com> In-Reply-To: <20261102-submit-h616-uart-fifo-v1-v6-0-25afcb346b0c@gmail.com> To: Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, James Hilliard X-Mailer: b4 0.15.2 The A523 UART integration, also used by A527 and T527, has 64-byte FIFOs on UART0 and 128-byte FIFOs on UART1 through UART7. Each controller reports its TX/RX FIFO depth in bits 31:8 of the FIFO Clock Control register at offset 0xf0. The field holds a byte count, not a logarithmic encoding. Read this field in the sunxi setup callback when platform data does not provide a fixed FIFO size. A fixed size takes precedence, so H616 retains its 256-byte configuration without accessing FCC. The probe has already enabled the clocks and deasserted reset before invoking the callback. Leave the FIFO clock-control bits untouched. Validate the depth before generating the RX trigger table or setting the transmit load. The quarter-full threshold must be positive and the FIFO-depth-minus-two threshold must fit in the byte-sized table and RX trigger API. Report an invalid depth and fail probe instead of generating zero or truncated thresholds. This bound follows the current 8250 table and callback types, not a hardware FIFO-capacity limit; support for larger thresholds would require widening that interface. Select this setup for the A523 compatible. Derive the transmit load and RX threshold table from the discovered depth using the common sunxi helpers. This handles the different FIFO sizes with one compatible and one receive-trigger mapping. Like H616, this integration has Allwinner-specific debug-divisor and RS485 registers overlapping the generic DesignWare feature probes. Use the common sunxi PIO setup, BUSY-safe integer divisor programming and software RS485 handling. Keep the APB clock gate enabled during termios updates with SKIP_SET_RATE. Signed-off-by: James Hilliard --- drivers/tty/serial/8250/8250_dw.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index 0b0156464af6..0ed50d9515e7 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -51,6 +52,10 @@ #define SUNXI_UART_RXTRIG_HALF_DIV 2 #define SUNXI_UART_RXTRIG_FULL_MARGIN 2 +/* Allwinner FIFO Clock Control register */ +#define SUNXI_UART_FCC 0xf0 +#define SUNXI_UART_FCC_FIFO_DEPTH GENMASK(31, 8) + /* Quirks */ #define DW_UART_QUIRK_OCTEON BIT(0) #define DW_UART_QUIRK_ARMADA_38X BIT(1) @@ -70,6 +75,7 @@ struct dw8250_platform_data { u8 usr_reg; u32 cpr_value; + /* Fixed FIFO depth; zero selects discovery during setup */ unsigned int fifo_size; unsigned int quirks; int (*setup)(struct uart_port *p); @@ -735,6 +741,20 @@ static int dw8250_sunxi_setup(struct uart_port *p) p->type = PORT_16550A; p->flags |= UPF_FIXED_TYPE; p->fifosize = data->pdata->fifo_size; + if (!p->fifosize) { + u32 fcc = dw8250_readl_ext(p, SUNXI_UART_FCC); + + p->fifosize = FIELD_GET(SUNXI_UART_FCC_FIFO_DEPTH, fcc); + } + /* + * The byte-sized 8250 RX trigger interface requires positive, + * representable thresholds. Larger thresholds require widening it. + */ + if (p->fifosize < SUNXI_UART_RXTRIG_QUARTER_DIV || + p->fifosize - SUNXI_UART_RXTRIG_FULL_MARGIN > U8_MAX) + return dev_err_probe(p->dev, -EINVAL, + "invalid FIFO size %u\n", p->fifosize); + up->capabilities = UART_CAP_FIFO | UART_CAP_NOTEMT | UART_CAP_AFE; dw8250_sunxi_setup_rxtrig(p); @@ -978,6 +998,12 @@ static const struct dw8250_platform_data dw8250_h616_data = { .setup = dw8250_sunxi_setup, }; +static const struct dw8250_platform_data dw8250_a523_data = { + .usr_reg = DW_UART_USR, + .quirks = DW_UART_QUIRK_SKIP_SET_RATE, + .setup = dw8250_sunxi_setup, +}; + static const struct dw8250_platform_data dw8250_octeon_3860_data = { .usr_reg = OCTEON_UART_USR, .quirks = DW_UART_QUIRK_OCTEON, @@ -1030,6 +1056,7 @@ static const struct dw8250_platform_data dw8250_tda54 = { static const struct of_device_id dw8250_of_match[] = { { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb }, { .compatible = "allwinner,sun50i-h616-uart", .data = &dw8250_h616_data }, + { .compatible = "allwinner,sun55i-a523-uart", .data = &dw8250_a523_data }, { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data }, { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, -- 2.53.0