From: Luo Liu <Luo.Liu@cixtech.com>
To: vkoul@kernel.org, neil.armstrong@linaro.org, mani@kernel.org,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
gary.yang@cixtech.com, fugang.duan@cixtech.com,
linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: cix-kernel-upstream@cixtech.com, p.zabel@pengutronix.de,
linux-kernel@vger.kernel.org, Luo.Liu@cixtech.com,
Wuyi.Shen@cixtech.com, EastLake.Yang@cixtech.com
Subject: [PATCH v4 0/3] phy: cix: Add Sky1 DisplayPort PHY support
Date: Mon, 2 Nov 2026 11:04:22 +0800 [thread overview]
Message-ID: <20261102030425.1957585-1-Luo.Liu@cixtech.com> (raw)
Add dt-bindings, driver and DTS support for the dedicated DisplayPort
PHY on the CIX Sky1 SoC.
The PHY exposes a PMA/CDB register interface and is controlled through
the generic PHY DP configure ops (link rate, lane count, SSC and
voltage swing). The APB clock is shared with the DPTx controller; the
PHY driver enables it around init/exit together with the hardware
reset.
Patch 1 adds the binding and MAINTAINERS entry.
Patch 2 adds the PHY driver.
Patch 3 describes the SoC node and enables it on Radxa Orion O6.
Changes in v4:
- Keep cix,external-dp for the external connector swing table
- Require clocks/clock-names ("apb"); wire CLK_TREE_DPC2_APBCLK
- Enable and disable the shared APB clock in phy_init/phy_exit
- Update copyright years to 2026
- Move bool members to the end of struct cix_dp
- Move the lane-count and timeout macros out of the register block
- Add CIX_DP_CDB_ENABLE_BIT instead of writing 1
- Drop the power_on/power_off dp->powered check; the PHY core already
refcounts those calls. The flag remains so link-rate updates know
whether the PLL is running
- Pick up Reviewed-by from Rob Herring
Changes in v3:
- Rename cix,external-dp to cix,edp (select eDP vs DP swing table)
- Restore TX_DIAG_ACYA on cix_dp_phy_set_lane_voltage() error paths
- Note that the PHY APB clock is managed by the DPTx driver
Changes in v2:
- Move MAINTAINERS into the binding patch; keep tabs; add R: entry
- Require resets; use exclusive reset in the driver
- Include linux/property.h; document Sky1 1/2-lane physical routing
- Rename DT label to dp_phy; enable it on sky1-orion-o6
- After CDB_ENABLE, wait for busy then idle to avoid a stale READY race
Luo Liu (3):
dt-bindings: phy: Add CIX Sky1 DP PHY
phy: cix: Add Sky1 DP PHY driver
arm64: dts: cix: Add Sky1 DP PHY node
.../bindings/phy/cix,sky1-dp-phy.yaml | 67 ++
MAINTAINERS | 8 +
arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 4 +
arch/arm64/boot/dts/cix/sky1.dtsi | 10 +
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/cix/Kconfig | 18 +
drivers/phy/cix/Makefile | 2 +
drivers/phy/cix/phy-cix-dp.c | 1004 +++++++++++++++++
9 files changed, 1115 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/cix,sky1-dp-phy.yaml
create mode 100644 drivers/phy/cix/Kconfig
create mode 100644 drivers/phy/cix/Makefile
create mode 100644 drivers/phy/cix/phy-cix-dp.c
base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
--
2.25.1
next reply other threads:[~2026-11-02 3:04 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-02 3:04 Luo Liu [this message]
2026-11-02 3:04 ` [PATCH v4 1/3] dt-bindings: phy: Add CIX Sky1 DP PHY Luo Liu
2026-11-02 3:04 ` [PATCH v4 2/3] phy: cix: Add Sky1 DP PHY driver Luo Liu
2026-11-02 3:04 ` [PATCH v4 3/3] arm64: dts: cix: Add Sky1 DP PHY node Luo Liu
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