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[2a02:3100:a9d0:ff01:e89e:fc6e:8de:7401]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4abebe33e79sm179710785e9.2.2026.11.01.20.12.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 01 Nov 2026 20:12:49 -0800 (PST) From: Karl Mehltretter To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Karl Mehltretter , Alexandre Ghiti , Andreas Schwab , "Maciej W. Rozycki" , Nam Cao , Zishun Yi , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] riscv: traps: Fix si_addr in misaligned access SIGBUS Date: Mon, 2 Nov 2026 05:12:37 +0100 Message-Id: <20261102041237.80873-1-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit do_trap_misaligned() sends SIGBUS with BUS_ADRALN when the kernel does not complete a misaligned access from user space, for example with PR_UNALIGN_SIGBUS. It passes regs->epc as the fault address, so si_addr holds the program counter, or 0 after a fault during emulation, instead of the address of the access. POSIX defines si_addr for SIGBUS as the address of the faulting memory reference. Pass regs->badaddr instead. Fixes: 76d2a0493a17 ("RISC-V: Init and Halt Code") Signed-off-by: Karl Mehltretter --- Assisted by an LLM. Tested on QEMU's virt machine (d73149283205, -cpu rv64,zicclsm=false) with OpenSBI v1.8.1. The kernels are abf8c33470f7, built with clang 22 from defconfig plus NONPORTABLE and RISCV_SBI_FWFT_DELEGATE_MISALIGNED. Not tested on real hardware. The test takes SIGBUS for lw and sw crossing into an unmapped page, lw with PR_UNALIGN_SIGBUS, and amoswap.w. With this patch, si_addr is the misaligned address in all four. Before it, si_addr is 0 for the first two and the PC for the others. The first two still report PC 0 in the ucontext. That separate bug is fixed by Zishun Yi's pending patch: https://lore.kernel.org/r/20260511124101.3202094-1-vulab@iscas.ac.cn/ arch/riscv/kernel/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index f8292adda0..0af1cdb352 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -225,7 +225,7 @@ static void do_trap_misaligned(struct pt_regs *regs, enum misaligned_access_type } if (misaligned_handler[type].handler(regs)) - do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc, + do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->badaddr, misaligned_handler[type].type_str); if (user_mode(regs)) { base-commit: abf8c33470f78e2226ee3dcdc69004660020ab47 -- 2.39.5 (Apple Git-154)