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Sun, 01 Nov 2026 23:22:27 -0800 (PST) Received: from localhost.localdomain ([103.178.205.93]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36a428af1dfsm36376021eec.7.2026.11.01.23.22.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Nov 2026 23:22:27 -0800 (PST) From: Sreeraj S Kurup To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, vkoul@kernel.org, neil.armstrong@linaro.org, mani@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Sreeraj S Kurup Subject: [PATCH] phy: mediatek: mt8195: Check PLL driver setting return value Date: Mon, 2 Nov 2026 07:21:39 +0000 Message-ID: <20261102072139.3588-1-sreekuttan2156239@gmail.com> X-Mailer: git-send-email 2.55.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The mtk_hdmi_pll_drv_setting() function can return -EINVAL when the requested pixel clock is outside its supported range. Currently, mtk_hdmi_pll_prepare() ignores this return value and continues with PLL initialization even when the driver settings fail. Check the return value and abort PLL preparation on failure to avoid powering up the PLL with invalid driver settings. Signed-off-by: Sreeraj S Kurup --- drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c index a4bc1268946d..9658781484f1 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c @@ -360,6 +360,7 @@ static int mtk_hdmi_pll_prepare(struct clk_hw *hw) { struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); void __iomem *regs = hdmi_phy->regs; + int ret; mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV_EN); @@ -374,7 +375,9 @@ static int mtk_hdmi_pll_prepare(struct clk_hw *hw) mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D2_EN); mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_CK_EN); - mtk_hdmi_pll_drv_setting(hw); + ret = mtk_hdmi_pll_drv_setting(hw); + if (ret) + return ret; mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BG_PWD); mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_BIAS_EN); -- 2.55.0