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Each PHY node describes its USB and DisplayPort lanes as child nodes, points at the S5 system controller instance that controls lane muxing and plug orientation, and is disabled by default so that boards that do not route the port stay unaffected. Reviewed-by: Fugang Duan Signed-off-by: Gary Yang --- arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 28 +++++++ arch/arm64/boot/dts/cix/sky1.dtsi | 96 +++++++++++++++++++++++ 2 files changed, 124 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts index e39c87774c12..76f75185b6a8 100644 --- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts +++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts @@ -117,3 +117,31 @@ &s5_gpio2 { &uart2 { status = "okay"; }; + +&usbc_phy0 { + orientation-switch; + mode-switch; + cix,default-conf = /bits/ 8 <0x03>; + status = "okay"; +}; + +&usbc_phy1 { + orientation-switch; + mode-switch; + cix,default-conf = /bits/ 8 <0x03>; + status = "okay"; +}; + +&usbc_phy2 { + orientation-switch; + mode-switch; + cix,default-conf = /bits/ 8 <0x03>; + status = "okay"; +}; + +&usbc_phy3 { + orientation-switch; + mode-switch; + cix,default-conf = /bits/ 8 <0x03>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index 0a820f45feb9..672aade42d6f 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -606,6 +606,102 @@ mbox_ap2sfh: mailbox@80a0000 { cix,mbox-dir = "tx"; }; + usbc_phy0: usb-phy@9030000 { + compatible = "cix,sky1-usbdp-phy"; + reg = <0x00 0x9030000 0x00 0x40000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk CLK_TREE_USB3C_DRD_PHY3_GATE>; + resets = <&s5_syscon SKY1_USB_DP_PHY0_RST_N>, + <&s5_syscon SKY1_USB_DP_PHY0_PRST_N>; + reset-names = "core", "apb"; + cix,usbphy-syscon = <&s5_syscon 0>; + + status = "disabled"; + + usb3_phy0: usb-port@0 { + reg = <0x0>; + #phy-cells = <0>; + }; + + usbc0_dp_phy: dp-port@1 { + reg = <0x1>; + #phy-cells = <0>; + }; + }; + + usbc_phy1: usb-phy@90a0000 { + compatible = "cix,sky1-usbdp-phy"; + reg = <0x00 0x90a0000 0x00 0x40000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk CLK_TREE_USB3C_0_PHY3_GATE>; + resets = <&s5_syscon SKY1_USB_DP_PHY1_RST_N>, + <&s5_syscon SKY1_USB_DP_PHY1_PRST_N>; + reset-names = "core", "apb"; + cix,usbphy-syscon = <&s5_syscon 1>; + + status = "disabled"; + + usb3_phy1: usb-port@0 { + reg = <0x0>; + #phy-cells = <0>; + }; + + usbc1_dp_phy: dp-port@1 { + reg = <0x1>; + #phy-cells = <0>; + }; + }; + + usbc_phy2: usb-phy@9110000 { + compatible = "cix,sky1-usbdp-phy"; + reg = <0x00 0x9110000 0x00 0x40000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk CLK_TREE_USB3C_1_PHY3_GATE>; + resets = <&s5_syscon SKY1_USB_DP_PHY2_RST_N>, + <&s5_syscon SKY1_USB_DP_PHY2_PRST_N>; + reset-names = "core", "apb"; + cix,usbphy-syscon = <&s5_syscon 2>; + + status = "disabled"; + + usb3_phy2: usb-port@0 { + reg = <0x0>; + #phy-cells = <0>; + }; + + usbc2_dp_phy: dp-port@1 { + reg = <0x1>; + #phy-cells = <0>; + }; + }; + + usbc_phy3: usb-phy@9180000 { + compatible = "cix,sky1-usbdp-phy"; + reg = <0x00 0x9180000 0x00 0x40000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk CLK_TREE_USB3C_2_PHY3_GATE>; + resets = <&s5_syscon SKY1_USB_DP_PHY3_RST_N>, + <&s5_syscon SKY1_USB_DP_PHY3_PRST_N>; + reset-names = "core", "apb"; + cix,usbphy-syscon = <&s5_syscon 3>; + + status = "disabled"; + + usb3_phy3: usb-port@0 { + reg = <0x0>; + #phy-cells = <0>; + }; + + usbc3_dp_phy: dp-port@1 { + reg = <0x1>; + #phy-cells = <0>; + }; + }; + pcie_x8_rc: pcie@a010000 { compatible = "cix,sky1-pcie-host"; reg = <0x00 0x0a010000 0x00 0x10000>, -- 2.50.1