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Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by TY2PEPF0000AB87.mail.protection.outlook.com (10.167.253.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.592.5 via Frontend Transport; Mon, 2 Nov 2026 08:21:13 +0000 Received: from gary-System-Product-Name (unknown [172.16.64.55]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 8B33D4102B63; Mon, 2 Nov 2026 16:21:12 +0800 (CST) From: Gary Yang To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Fugang Duan Cc: CIX Linux Kernel Upstream Group , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gary Yang Subject: [PATCH 1/3] dt-bindings: phy: add CIX Sky1 USB/DP combo PHY Date: Mon, 2 Nov 2026 16:21:10 +0800 Message-ID: <20261102082112.2306326-2-gary.yang@cixtech.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20261102082112.2306326-1-gary.yang@cixtech.com> References: <20261102082112.2306326-1-gary.yang@cixtech.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB87:EE_|SE3PR06MB8014:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 42703adf-a733-4fcd-05a1-08df38ba424a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|23010399003|376014|7416014|36860700016|82310400026|56012099006|261009223027099003|261028144727099003|261021121427099003|261026121527099003|261026140227099003|261022075727099003|261022105027099003|10067099003|20046099003|18002099003|22082099003|6133799003|3023799007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: b529ACyQnog803z8fBE7pZO7kFiP5xEl9uVwsRd+xC5e3+atkQBVjDbVZTfeixqjOFtp7cjdh/kKCsIhChY37iTWBdDYzKdgv2AyKDi0gzOwsfFei9eipZLs0arFRRnj0FzSIUAOTTskAhzZke+q80nDu3Xeg24K56fNX+cdvKK/GLvzUTOpUM/6G2BrcGEha9GIeYjvKhqn81GxP25RKc/252R55Gv4Cx9wCmQuF+GHZIww2E+FHfy1Kx0ucxbS3e/hHsL7peiQiUio1zU2mRbkMCgy9N7UzqAe9Ye+vCp8w36PhLpZpGzFtVrqWGR4YcR2LWVCLDcTE7sp5zc6BZKSfQzk9Jqo8vAvnjtFpUqVsrEpFu8UKaXbjDxTpjrEObUrofWDbdqmDpIy1h0tFVl3HwgOwprFr1WrTS8PZhOl9Wo0EbUCpjTJ6hH0cymD X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Nov 2026 08:21:13.3957 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 42703adf-a733-4fcd-05a1-08df38ba424a X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB87.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SE3PR06MB8014 Document the USB/DP combo PHY of the CIX Sky1 SoC. Each PHY instance exposes one SuperSpeedPlus USB lane and one DisplayPort lane as child nodes, so that the USB and DP consumers can each reference the lane they use. The PHY performs Type-C plug orientation switching and USB/DP lane muxing in hardware and is therefore described with the "orientation-switch" and "mode-switch" properties. Lane muxing is programmed through the S5 system controller, identified by the "cix,usbphy-syscon" phandle followed by the PHY instance index. Reviewed-by: Fugang Duan Signed-off-by: Gary Yang --- .../bindings/phy/cix,sky1-usbdp-phy.yaml | 150 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 151 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/cix,sky1-usbdp-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/cix,sky1-usbdp-phy.yaml b/Documentation/devicetree/bindings/phy/cix,sky1-usbdp-phy.yaml new file mode 100644 index 000000000000..a5b6943f84eb --- /dev/null +++ b/Documentation/devicetree/bindings/phy/cix,sky1-usbdp-phy.yaml @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/cix,sky1-usbdp-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CIX Sky1 USB/DP Combo PHY + +maintainers: + - Gary Yang + +description: + The CIX Sky1 USB/DP combo PHY provides one SuperSpeedPlus USB lane + and one DisplayPort lane for a USB3C Type-C port. The USB and DP + lanes are represented as child nodes of the PHY controller. + +properties: + compatible: + const: cix,sky1-usbdp-phy + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + clocks: + maxItems: 1 + description: PHY APB clock. + + resets: + items: + - description: PHY core reset + - description: PHY APB preset + + reset-names: + items: + - const: core + - const: apb + + orientation-switch: + description: + The PHY handles Type-C plug orientation switching. + type: boolean + + mode-switch: + description: + The PHY handles multiplexing of the USB and DisplayPort lanes. + type: boolean + + cix,usbphy-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the S5 system controller + - description: PHY instance index within the system controller + description: + Phandle to the system controller used for lane muxing and + Type-C orientation control, followed by the PHY instance index. + + cix,default-conf: + $ref: /schemas/types.yaml#/definitions/uint8 + enum: [0, 1, 2, 3] + default: 3 + description: | + Lane mode the PHY is put in until a consumer changes it through the + Type-C mux. The value is a bit mask: 0 = none, 1 = USB, 2 = DP, + 3 = USB and DP. + +patternProperties: + "^usb-port@[0-9a-f]+$": + type: object + description: + The USB lane of the combo PHY. + + properties: + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + required: + - reg + - "#phy-cells" + + additionalProperties: false + + "^dp-port@[0-9a-f]+$": + type: object + description: + The DisplayPort lane of the combo PHY. + + properties: + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + required: + - reg + - "#phy-cells" + + additionalProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - clocks + - resets + - reset-names + - cix,usbphy-syscon + +additionalProperties: false + +examples: + - | + #include + #include + + usbc_phy0: usb-phy@9030000 { + compatible = "cix,sky1-usbdp-phy"; + reg = <0x09030000 0x40000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk CLK_TREE_USB3C_DRD_PHY3_GATE>; + resets = <&s5_syscon SKY1_USB_DP_PHY0_RST_N>, + <&s5_syscon SKY1_USB_DP_PHY0_PRST_N>; + reset-names = "core", "apb"; + cix,usbphy-syscon = <&s5_syscon 0>; + cix,default-conf = /bits/ 8 <0x03>; + orientation-switch; + mode-switch; + + usb-port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + dp-port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 93abbb315065..8fb940a3ea3b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2903,6 +2903,7 @@ S: Maintained T: git https://github.com/cixtech/linux-mainline.git F: Documentation/devicetree/bindings/arm/cix.yaml F: Documentation/devicetree/bindings/mailbox/cix,sky1-mbox.yaml +F: Documentation/devicetree/bindings/phy/cix,sky1-usbdp-phy.yaml F: arch/arm64/boot/dts/cix/ F: drivers/mailbox/cix-mailbox.c K: \bcix\b -- 2.50.1