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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4b6yJMujTP+Kpia0kqYG2zR2E+7yfPauGOuGM8KmYysbG05EON8VvjXgecNEuYmxtVgl243dEJe4saiev1RopjTO22z+ByjOSxzl4Ac7gJ/IaYvWrI7/cnuc0s6mMX72y3YiE6ivxw7VIenJEwzrf+l6DIefG7ZF/15TWzFl+Ar+dzyoVCpsWoUIUA+f6pg+9PZQlHCYunXihC+wQopOlwLwC6lfbztyeQ6bQw6BekJq0bN4OPmrXCX9WKC5LFdoe6ofm2G8ZAWvnZ73Dz0srVXi+M4ifmlkfa1iN0NmxjbDgpXbSXXwSK7D7w7CiWZb0SMhudku3vEq5EGtenKIZFasNH1tXg1+WinCj29yVKZFxzLxNXU7Pqz6+VCWmbDa95cJtUT3MCfTxeemL7r0AwAzuz9qJgVAaZWmXDoqB171qm9etXSKzFx3B0K8CdD9 X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Nov 2026 08:41:54.1791 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0f8290ec-d6bf-40fd-1ee1-08df38bd25c4 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E3.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYNPR06MB8880 From: "Johnny.Fan" This series makes SPE and TRBE usable on heterogeneous ACPI systems, where not all CPUs implement the feature and the ones that do may use different PPIs. The MADT describes both per CPU, and the PPTT hetero id tells identical implementations apart. Patch 1 lets the drivers take the CPU mask from platform data; patch 2 creates one platform device per (hetero id, interrupt) group and passes the mask along. v2: https://lore.kernel.org/all/20261021020322.3015121-1-johnny.fan@cixtech.com/ Changes since v2: - Split into two patches: drivers first (no functional change), then the ACPI producer. This keeps every patch bisectable; with the opposite order an intermediate kernel would create devices whose CPU mask falls back to cpu_possible_mask and probe CPUs that do not implement the feature. - Reject GICC entries with inconsistent lengths instead of silently skipping them, while still treating tables that never describe the field (pre-ACPI 6.3 for SPE, 6.5 for TRBE) as "feature absent". - Allocate the groups dynamically instead of a possible-CPUs-sized array; the counting pass remains as the firmware consistency check. - Only release a shared GSI once no successfully registered device uses it, fixing the mapping leak when every group on that GSI fails. On Leo's question about exposing the mask through platform_get_irq_affinity(): these devices are synthetic and have no fwnode, so the lookup falls back to cpu_possible_mask. The mask is a property of the device, not of the interrupt: a GSI can be shared by groups with disjoint CPU masks, so a per-interrupt affinity would be wrong for each of them. ACPI cannot describe PPI affinity today anyway. Johnny.Fan (2): perf: arm_pmu: Accept a per-device CPU mask from platform data perf: arm_pmu_acpi: Support heterogeneous ACPI systems drivers/hwtracing/coresight/coresight-trbe.c | 22 +- drivers/perf/arm_pmu_acpi.c | 238 +++++++++++++------ drivers/perf/arm_spe_pmu.c | 10 +- include/linux/perf/arm_pmu.h | 10 + 4 files changed, 205 insertions(+), 75 deletions(-) -- 2.55.0