Re: [PATCH net] net: stmmac: dwmac-motorcomm: mask the MISC interrupt

[Magnus Leatti <magnusleatti@kernelriot.com>]

Hi Nicolai,

On 11/2/26 09:29, Nicolai Buchwitz wrote:
>> +#define  MGMT_INT_CTRL0_MASK_MISC		BIT(21)
> 
> Where is this bit documented? The vendor driver?

Yes. The vendor driver writes 0x00200000 there unless it services MISC
itself, and the yt6801 driver Motorcomm posted in 2025 defines the mask
field as bits 16-31 of MGMT_INT_CTRL0, with MISC as status bit 5.

>> +	writel(MGMT_INT_CTRL0_MASK_MISC, priv->base + MGMT_INT_CTRL0);
> 
> Doesn't this turn off the stmmac MAC irq on vector 5 completely? If so,
> please mention it in the comment.

Yes. On this device vector 5 only carries MISC. I should have said so.

> Also, does the MSI fallback still get RX/TX interrupts with MISC masked?

RX and TX have their own mask bits, but I did not test the single-MSI
path.

Maxime's patch fixes the hang here without the mask, so I have asked
for this one to be dropped.

Thanks for jumping on this so quickly, Maxime and Nicolai! I really
appreciate it. Have a good Monday :)

Magnus