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Mon, 2 Nov 2026 09:17:02 +0000 (GMT) Received: from li-fbf77acc-29ba-11b2-a85c-e8e934f50a46.ibmuc.com (unknown [9.39.25.78]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 2 Nov 2026 09:17:02 +0000 (GMT) From: Gautam Menghani To: maddy@linux.ibm.com, npiggin@gmail.com, mpe@ellerman.id.au, chleroy@kernel.org, ritesh.list@gmail.com, sshegde@linux.ibm.com Cc: linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Timothy Pearson Subject: [PATCH v5] KVM: PPC: Book3S HV: Avoid spurious interrupts caused by LPCR_MER bit Date: Mon, 2 Nov 2026 14:46:59 +0530 Message-ID: <20261102091700.253381-1-gautam@linux.ibm.com> X-Mailer: git-send-email 2.56.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-ORIG-GUID: 1xCTqIO-R6O4I7UknL9LItpBB8SQ9GdA X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTAyMDAzNiBTYWx0ZWRfX+e9PO0TL10Qz hjS+vaFzr07I4waGgYsF0T62LrURQ23/hWlf1e+Entqw2NlPHpU/UyqUBwWf5PoMghNwbq23uXI YqE6bTHgUon4ekUsn9Qvoa7fGXgAKfo+zryPGxL+XAYqqqNPBK+RBA5axp7NJT9qmjoY+EfN1OX PNLyjhUhf0lg0yIEOoa4Df81yxLi7FSSN6K7k5j9sMsvKIlfw3htCq2vHPrzgKKArgHBUnGXOni q7jE6sOYPXjpxzg0pK7Bq9NG20ad6xKyH6fiICKiQ8GN+qesP1KYHZvpMuR4aGenwZISi5iUjbN 5md5E9TliAgbKuiFe1UiJ4CgZhENTytoHnWrIIzLTQ72XeXbzrYilu9TMozDlVQbhBNEDCfzJwu EDa8jtVPpubCa7upn9fKjLSjTmPrmn/Gh/7IsbO4vT+DDV4isCsHYZ08281YpvNhimW0pBDZZZa kqt3/hlwFEHr/QcouuA== X-Proofpoint-Spam-Info: AW1haW4tMjYxMTAyMDAzNiBTYWx0ZWRfX1DGZSkJsc4A/ /WKJQqnyTmCenyBToPYHCAoBM5Fb33J012nTyqMEHkHuXrpWSPk5AQuI0W/VSGDjdDnFVwnbzUx gt6fTYnZbfxswNOObOe6ud7SyARv5/k= X-Proofpoint-GUID: sODIPSMf0RgplZhJwFRSOSvwSs2E-GtE X-Authority-Analysis: v=2.4 cv=EsJHPicA c=1 sm=1 tr=0 ts=6ae85516 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=zJRp6_cAMcgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=VwQbUJbxAAAA:8 a=yKAn6K1XAAAA:8 a=_AprYWD3AAAA:8 a=VnNF1IyMAAAA:8 a=r95I5fjiukzm4VaaYucA:9 a=6M1ixcW_PCWoKiWyFx5v:22 a=fKH2wJO7VO9AkD4yHysb:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-02_03,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 priorityscore=1501 adultscore=0 impostorscore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611020036 A huge number of spurious interrupts can be seen immediately after a KVM on PowerNV guest boots up in XIVE mode. $ cat /proc/interrupts | grep SPU SPU: 223705 192439 273526 147623 Spurious interrupts This bug was introduced by commit ecd10702baae5 ("KVM: PPC: Book3S HV: Handle pending exceptions on guest entry with MSR_EE"). The root cause is that once LPCR_MER bit is set, it is supposed to be reset by software. But when a vCPU starts running with LPCR_MER set, the vCPU does not exit back to the host until the decrementer expires or there is an hcall, etc. This is because KVM on PowerNV guests have support for native XIVE, so they are not dependent on host for interrupt emulation. Due to this behaviour, a huge number of spurious interrupts are seen since LPCR_MER continues to be set and LPCR_MER cannot be reset until the vCPU exits to the host. Fix this behaviour by not using the LPCR_MER bit whenever native XIVE is available (currently in case of KVM on PowerNV only), as the XIVE hardware can present interrupts to the KVM guest vCPU directly. So the LPCR_MER functionality is not required. This reduces the number of spurious interrupts drastically. Fixes: ecd10702baae5 ("KVM: PPC: Book3S HV: Handle pending exceptions on guest entry with MSR_EE") Cc: stable@vger.kernel.org # 6.8+ Reported-by: Timothy Pearson Closes: https://lore.kernel.org/linuxppc-dev/582904882.11159.1786719390349.JavaMail.zimbra@raptorengineeringinc.com Signed-off-by: Gautam Menghani --- v5: 1. Drop the redundant check for the presence of the native XIVE device. (Ritesh) v4: 1. If interrupt mode is changed to XICS during guest reboot, MER should be used. (Amit) v3: 1. Continue the use of LPCR_MER when kernel-irqchip=off (Sashiko) v2: 1. Handle the case where xive_interrupt_pending() is true and also the external exception bit is set. (Narayana) arch/powerpc/kvm/book3s_hv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index 22283d46e8fe..41012b0accf4 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -4984,7 +4984,7 @@ int kvmhv_run_single_vcpu(struct kvm_vcpu *vcpu, u64 time_limit, if (!kvmhv_on_pseries() && (__kvmppc_get_msr_hv(vcpu) & MSR_EE)) kvmppc_inject_interrupt_hv(vcpu, BOOK3S_INTERRUPT_EXTERNAL, 0); - else + else if (!kvmppc_xive_enabled(vcpu)) lpcr |= LPCR_MER; } else { /* -- 2.55.0