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Mon, 2 Nov 2026 01:23:02 -0800 From: Manikanta Maddireddy To: , , , , , CC: , , , , , , , Subject: [PATCH v3 2/2] PCI: dwc: Consolidate RAS-DES event counter fields Date: Mon, 2 Nov 2026 14:52:38 +0530 Message-ID: <20261102092238.3917883-3-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261102092238.3917883-1-mmaddireddy@nvidia.com> References: <20261102092238.3917883-1-mmaddireddy@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000037A3:EE_|SN7PR12MB7787:EE_ X-MS-Office365-Filtering-Correlation-Id: 65ce4170-be0a-4a3a-47f3-08df38c2f0ec X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|23010399003|376014|7416014|1800799024|10067099003|22082099003|18002099003|56012099006|11063799006|261021121427099003|261021123027099003|261022075727099003|261009223027099003; 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Signed-off-by: Manikanta Maddireddy --- .../controller/dwc/pcie-designware-debugfs.c | 40 +++++++------------ drivers/pci/controller/dwc/pcie-designware.h | 4 ++ 2 files changed, 19 insertions(+), 25 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers/pci/controller/dwc/pcie-designware-debugfs.c index be0b84665c9e..eb899ed7d418 100644 --- a/drivers/pci/controller/dwc/pcie-designware-debugfs.c +++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c @@ -31,16 +31,6 @@ #define ERR_INJ_ENABLE_REG 0x30 -#define RAS_DES_EVENT_COUNTER_DATA_REG 0xc - -#define RAS_DES_EVENT_COUNTER_CTRL_REG 0x8 -#define EVENT_COUNTER_GROUP_SELECT GENMASK(27, 24) -#define EVENT_COUNTER_EVENT_SELECT GENMASK(23, 16) -#define EVENT_COUNTER_LANE_SELECT GENMASK(11, 8) -#define EVENT_COUNTER_STATUS BIT(7) -#define EVENT_COUNTER_ENABLE GENMASK(4, 2) -#define PER_EVENT_ON 0x3 -#define PER_EVENT_OFF 0x1 #define DWC_DEBUGFS_BUF_MAX 128 @@ -356,11 +346,11 @@ static void set_event_number(struct dwc_pcie_rasdes_priv *pdata, { u32 val; - val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG); - val &= ~EVENT_COUNTER_ENABLE; - FIELD_MODIFY(EVENT_COUNTER_GROUP_SELECT, &val, event_list[pdata->idx].group_no); - FIELD_MODIFY(EVENT_COUNTER_EVENT_SELECT, &val, event_list[pdata->idx].event_no); - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CONTROL); + val &= ~EVENT_COUNTER_ENABLE_MASK; + FIELD_MODIFY(EVENT_COUNTER_GROUP_SEL_MASK, &val, event_list[pdata->idx].group_no); + FIELD_MODIFY(EVENT_COUNTER_EVENT_SEL_MASK, &val, event_list[pdata->idx].event_no); + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CONTROL, val); } static ssize_t counter_enable_read(struct file *file, char __user *buf, @@ -375,7 +365,7 @@ static ssize_t counter_enable_read(struct file *file, char __user *buf, mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CONTROL); mutex_unlock(&rinfo->reg_event_lock); val = FIELD_GET(EVENT_COUNTER_STATUS, val); if (val) @@ -401,13 +391,13 @@ static ssize_t counter_enable_write(struct file *file, const char __user *buf, mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CONTROL); if (enable) - val |= FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_ON); + val |= FIELD_PREP(EVENT_COUNTER_ENABLE_MASK, EVENT_COUNTER_ENABLE_PER_EVENT); else - val |= FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_OFF); + val |= FIELD_PREP(EVENT_COUNTER_ENABLE_MASK, EVENT_COUNTER_DISABLE_PER_EVENT); - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val); + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CONTROL, val); /* * While enabling the counter, always read the status back to check if @@ -416,7 +406,7 @@ static ssize_t counter_enable_write(struct file *file, const char __user *buf, */ if (enable) { val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + - RAS_DES_EVENT_COUNTER_CTRL_REG); + RAS_DES_EVENT_COUNTER_CONTROL); if (!FIELD_GET(EVENT_COUNTER_STATUS, val)) { mutex_unlock(&rinfo->reg_event_lock); return -EOPNOTSUPP; @@ -440,7 +430,7 @@ static ssize_t counter_lane_read(struct file *file, char __user *buf, mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CONTROL); mutex_unlock(&rinfo->reg_event_lock); val = FIELD_GET(EVENT_COUNTER_LANE_SELECT, val); pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Lane: %d\n", val); @@ -463,9 +453,9 @@ static ssize_t counter_lane_write(struct file *file, const char __user *buf, mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CONTROL); FIELD_MODIFY(EVENT_COUNTER_LANE_SELECT, &val, lane); - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val); + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CONTROL, val); mutex_unlock(&rinfo->reg_event_lock); return count; @@ -483,7 +473,7 @@ static ssize_t counter_value_read(struct file *file, char __user *buf, mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_DATA_REG); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_DATA); mutex_unlock(&rinfo->reg_event_lock); pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter value: %d\n", val); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 6d788aa00011..09fb802174ee 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -276,7 +276,11 @@ #define RAS_DES_EVENT_COUNTER_CONTROL 0x8 #define EVENT_COUNTER_ALL_CLEAR 0x3 #define EVENT_COUNTER_ENABLE_ALL 0x7 +#define EVENT_COUNTER_ENABLE_PER_EVENT 0x3 +#define EVENT_COUNTER_DISABLE_PER_EVENT 0x1 #define EVENT_COUNTER_ENABLE_MASK GENMASK(4, 2) +#define EVENT_COUNTER_STATUS BIT(7) +#define EVENT_COUNTER_LANE_SELECT GENMASK(11, 8) #define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(23, 16) #define EVENT_COUNTER_GROUP_SEL_MASK GENMASK(27, 24) #define EVENT_COUNTER_EVENT_Tx_L0S 0x2 -- 2.34.1