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Mon, 02 Nov 2026 17:25:22 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Mon, 2 Nov 2026 17:25:20 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Mon, 2 Nov 2026 17:25:20 +0800 From: santino.wang To: Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , , Santino Wang Subject: [RFC PATCH 02/11] soc: mediatek: dram-ecc: add the SMC interface to the secure firmware Date: Mon, 2 Nov 2026 17:23:24 +0800 Message-ID: <20261102092334.138759-3-santino.wang@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20261102092334.138759-1-santino.wang@mediatek.com> References: <20261102092334.138759-1-santino.wang@mediatek.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-MTK: N From: Santino Wang The error containment policy and the CE storm protection are enforced by the secure firmware. Add helpers that read and write the corresponding settings through vendor-specific SMC calls, so the sysfs attributes added by later patches can configure them. Nothing calls these helpers yet. Signed-off-by: Santino Wang --- drivers/soc/mediatek/dram-ecc/core/Makefile | 3 +- drivers/soc/mediatek/dram-ecc/core/smc.c | 137 ++++++++++++++++++++ drivers/soc/mediatek/dram-ecc/core/smc.h | 55 ++++++++ 3 files changed, 194 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/mediatek/dram-ecc/core/smc.c create mode 100644 drivers/soc/mediatek/dram-ecc/core/smc.h diff --git a/drivers/soc/mediatek/dram-ecc/core/Makefile b/drivers/soc/mediatek/dram-ecc/core/Makefile index 77751c836027..429347bfd057 100644 --- a/drivers/soc/mediatek/dram-ecc/core/Makefile +++ b/drivers/soc/mediatek/dram-ecc/core/Makefile @@ -3,4 +3,5 @@ obj-$(CONFIG_MTK_DRAM_ECC) += mtk_dram_ecc.o mtk_dram_ecc-y := \ - main.o + main.o \ + smc.o diff --git a/drivers/soc/mediatek/dram-ecc/core/smc.c b/drivers/soc/mediatek/dram-ecc/core/smc.c new file mode 100644 index 000000000000..1f7a195d8b58 --- /dev/null +++ b/drivers/soc/mediatek/dram-ecc/core/smc.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2026 MediaTek Inc. + */ +#include +#include + +#include "smc.h" + +static int smc_set(u64 subcmd, u64 val) +{ + struct arm_smccc_res res; + + arm_smccc_smc(MTK_SIP_DRAM_ECC_SET_POLICY_AARCH64, + subcmd, val, 0, 0, 0, 0, 0, &res); + return (int)(long)res.a0; +} + +static int smc_get(u64 subcmd, u64 *val) +{ + struct arm_smccc_res res; + + arm_smccc_smc(MTK_SIP_DRAM_ECC_SET_POLICY_AARCH64, + subcmd, 0, 0, 0, 0, 0, 0, &res); + if ((int)(long)res.a0 != 0) + return (int)(long)res.a0; + *val = res.a1; + return 0; +} + +int mtk_dram_ecc_smc_containment_set_enabled(bool enabled) +{ + return smc_set(MTK_ECC_SMC_CONTAINMENT_SET_ENABLED, enabled ? 1 : 0); +} + +int mtk_dram_ecc_smc_containment_get_enabled(bool *enabled) +{ + u64 val; + int ret = smc_get(MTK_ECC_SMC_CONTAINMENT_GET_ENABLED, &val); + + if (!ret) + *enabled = (val != 0); + return ret; +} + +int mtk_dram_ecc_smc_containment_set_default_severity(bool recoverable) +{ + return smc_set(MTK_ECC_SMC_CONTAINMENT_SET_DEFAULT_SEVERITY, recoverable ? 1 : 0); +} + +int mtk_dram_ecc_smc_containment_get_default_severity(bool *recoverable) +{ + u64 val; + int ret = smc_get(MTK_ECC_SMC_CONTAINMENT_GET_DEFAULT_SEVERITY, &val); + + if (!ret) + *recoverable = (val != 0); + return ret; +} + +int mtk_dram_ecc_smc_storm_set_threshold(u32 val) +{ + return smc_set(MTK_ECC_SMC_STORM_SET_THRESHOLD, val); +} + +int mtk_dram_ecc_smc_storm_get_threshold(u32 *val) +{ + u64 v; + int ret = smc_get(MTK_ECC_SMC_STORM_GET_THRESHOLD, &v); + + if (!ret) + *val = (u32)v; + return ret; +} + +int mtk_dram_ecc_smc_storm_set_time_window(u32 val) +{ + return smc_set(MTK_ECC_SMC_STORM_SET_TIME_WINDOW, val); +} + +int mtk_dram_ecc_smc_storm_get_time_window(u32 *val) +{ + u64 v; + int ret = smc_get(MTK_ECC_SMC_STORM_GET_TIME_WINDOW, &v); + + if (!ret) + *val = (u32)v; + return ret; +} + +int mtk_dram_ecc_smc_storm_set_cooldown(u32 val) +{ + return smc_set(MTK_ECC_SMC_STORM_SET_COOLDOWN, val); +} + +int mtk_dram_ecc_smc_storm_get_cooldown(u32 *val) +{ + u64 v; + int ret = smc_get(MTK_ECC_SMC_STORM_GET_COOLDOWN, &v); + + if (!ret) + *val = (u32)v; + return ret; +} + +int mtk_dram_ecc_smc_range_add(u64 addr_from, u64 addr_to, bool recoverable) +{ + struct arm_smccc_res res; + + arm_smccc_smc(MTK_SIP_DRAM_ECC_SET_POLICY_AARCH64, MTK_ECC_SMC_RANGE_ADD, + addr_from, addr_to, recoverable ? 1 : 0, 0, 0, 0, &res); + return (int)(long)res.a0; +} + +int mtk_dram_ecc_smc_range_clear(void) +{ + struct arm_smccc_res res; + + arm_smccc_smc(MTK_SIP_DRAM_ECC_SET_POLICY_AARCH64, MTK_ECC_SMC_RANGE_CLEAR, + 0, 0, 0, 0, 0, 0, &res); + return (int)(long)res.a0; +} + +int mtk_dram_ecc_smc_range_get(u32 index, u64 *addr_from, u64 *addr_to, bool *recoverable) +{ + struct arm_smccc_res res; + + arm_smccc_smc(MTK_SIP_DRAM_ECC_SET_POLICY_AARCH64, MTK_ECC_SMC_RANGE_GET, + index, 0, 0, 0, 0, 0, &res); + if ((int)(long)res.a0 != 0) + return -ENOENT; + + *addr_from = res.a1; + *addr_to = res.a2; + *recoverable = (res.a3 != 0); + return 0; +} diff --git a/drivers/soc/mediatek/dram-ecc/core/smc.h b/drivers/soc/mediatek/dram-ecc/core/smc.h new file mode 100644 index 000000000000..712c01d28bf4 --- /dev/null +++ b/drivers/soc/mediatek/dram-ecc/core/smc.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2026 MediaTek Inc. + */ +#ifndef _MTK_DRAM_ECC_SMC_H_ +#define _MTK_DRAM_ECC_SMC_H_ + +#include + +#define MTK_SIP_DRAM_ECC_SET_POLICY_AARCH64 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, 0x542) + +/* + * Sub-commands for MTK_SIP_DRAM_ECC_SET_POLICY: + * x1 = sub-command + * x2 = payload + * return a0 = 0 on success, negative on error + * return a1 = value (GET commands only) + */ +enum mtk_dram_ecc_smc_subcmd { + MTK_ECC_SMC_CONTAINMENT_SET_ENABLED = 0, + MTK_ECC_SMC_CONTAINMENT_GET_ENABLED = 1, + MTK_ECC_SMC_CONTAINMENT_SET_DEFAULT_SEVERITY = 2, + MTK_ECC_SMC_CONTAINMENT_GET_DEFAULT_SEVERITY = 3, + MTK_ECC_SMC_STORM_SET_THRESHOLD = 4, + MTK_ECC_SMC_STORM_GET_THRESHOLD = 5, + MTK_ECC_SMC_STORM_SET_TIME_WINDOW = 6, + MTK_ECC_SMC_STORM_GET_TIME_WINDOW = 7, + MTK_ECC_SMC_STORM_SET_COOLDOWN = 8, + MTK_ECC_SMC_STORM_GET_COOLDOWN = 9, + MTK_ECC_SMC_STORM_SET_FORCE_REENABLE = 10, + MTK_ECC_SMC_RANGE_ADD = 11, + MTK_ECC_SMC_RANGE_CLEAR = 12, + MTK_ECC_SMC_RANGE_GET = 13, +}; + +int mtk_dram_ecc_smc_containment_set_enabled(bool enabled); +int mtk_dram_ecc_smc_containment_get_enabled(bool *enabled); +int mtk_dram_ecc_smc_containment_set_default_severity(bool recoverable); +int mtk_dram_ecc_smc_containment_get_default_severity(bool *recoverable); +int mtk_dram_ecc_smc_storm_set_threshold(u32 val); +int mtk_dram_ecc_smc_storm_get_threshold(u32 *val); +int mtk_dram_ecc_smc_storm_set_time_window(u32 val); +int mtk_dram_ecc_smc_storm_get_time_window(u32 *val); +int mtk_dram_ecc_smc_storm_set_cooldown(u32 val); +int mtk_dram_ecc_smc_storm_get_cooldown(u32 *val); + +/* addr_from/addr_to: [addr_from, addr_to) range, recoverable: false=fatal/true=recoverable. */ +int mtk_dram_ecc_smc_range_add(u64 addr_from, u64 addr_to, bool recoverable); +int mtk_dram_ecc_smc_range_clear(void); +/* Returns -ENOENT if index has no entry (also signals end-of-table). */ +int mtk_dram_ecc_smc_range_get(u32 index, u64 *addr_from, u64 *addr_to, bool *recoverable); + +#endif /* _MTK_DRAM_ECC_SMC_H_ */ -- 2.45.2