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Mon, 2 Nov 2026 03:27:31 -0800 From: Manikanta Maddireddy To: , , , , CC: , , , , , , , , , , , , Subject: [PATCH v3 00/10] PCI: tegra194: Fix EP and Root Port corner cases Date: Mon, 2 Nov 2026 16:57:09 +0530 Message-ID: <20261102112719.4022633-1-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000A894:EE_|IA0PR12MB8982:EE_ X-MS-Office365-Filtering-Correlation-Id: 6756cae0-64dc-4b48-7fab-08df38d455ba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|23010399003|1800799024|36860700016|82310400026|261021133027099003|11063799006|56012099006|261009223027099003|261028144727099003|261021123027099003|261021121427099003|261021130227099003|261021135927099003|261026135527099003|261026121527099003|261022115727099003|261022075727099003|261022105027099003|261026130827099003|261022113327099003|261026140227099003|10067099003|18002099003|6133799003|13003099007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 52tfzF/xsmCrv2N8VrXBcHMyKmRteJDKWoeeJGxuc6M4Lh/LxwpPyLHfKFESPq2IcPbQ0UJ72yqQZgreaUOgdGxdyxAbAJAMCJzsTxQxVDsVcPZ7yPBM2QDTFLwSNKG2FAynhTGHaAvzKkV2RYAMSvcM1li8wGtX/sOGCvhgDDJkKJrGxCjSKoY4kW4MNF12KqJOO/Ai2ALjAIhsCv535AuSk9JwBpPys+JOM0XC2+137+hsooQDORrmU8wCh+6kSUXB0gYrERq+nr/LJ7U6JWVRoxcKCT3bUhC2xYXPndXFUJruKiWDMdM4/hHmx4oGl6KDQiMziHofyGoJK0WvHAESBHi6EPer+fjmIhkkK0wsD2M65nsoVfOq3uaiCmZwbnSjISCyVFxrAYMchaLfXEhnAD/Z9eQ50LFWs5oOnHGe86exAy3eyprYK5foqN1U X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Nov 2026 11:27:53.0739 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6756cae0-64dc-4b48-7fab-08df38d455ba X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A894.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8982 This series fixes a set of independent Tegra194/Tegra234 PCIe controller issues found while testing Root Port and Endpoint flows. The Root Port fixes tighten probe/remove and suspend/resume error handling: propagate optional GPIO failures, check reset deassertion, avoid skipping cleanup when no link came up, and enable the optional core monitor clock only after link setup and final core clock rate selection. The Endpoint fixes cover PERST# IRQ suspend handling, PHY/PLL error unwinds, capability checks before programming optional PCIe extended capabilities, hiding Tegra234 EP L1.2 advertisement for the documented hardware limitation, and rejecting invalid MSI interrupt number zero. The patches are ordered from low-level error handling toward Endpoint capability checks and MSI validation. MSI-X enablement, MSI-X doorbell changes and fixed MSI-X table handling are deferred; MSI-X remains disabled in the Tegra EPC features. Changes in v3: - Rebase onto the current PCI main-based stack after the DWC register-field cleanup series. Patches 1-8 and 10 have no code changes from v2. - Rework patch 9 and rename it to "Enable core monitor clock after link setup". Set the core clock rate to 500 MHz before enabling it, program the controller, train the link, select the negotiated-speed core rate, and then enable the monitor clock. - Propagate initial and negotiated core rate-setting errors and monitor enable failures. Keep monitor operations out of the host initialization callback and DLF retry path, and release the monitor during remove, suspend and shutdown without a separate reference-state flag. - Expand patch 9's explanation of the Boot and Power Management Processor (BPMP) firmware voltage requirement and false frequency-monitor faults during rate transitions. - Retain Frank Li's Reviewed-by tags from v2 on unchanged patches 1-8 and 10. Changes in v2: - Expand the PERST# suspend-race explanation to describe how an IRQ thread can enable the endpoint after the original state check. Explain how disable_irq() drains that thread and preserves the existing suspend policy, and add a synchronization comment. - Split the MSI-only zero check out of the former MSI/MSI-X patch, with a focused title and commit message. Treat it as defensive validation and omit the Fixes tag from that patch. - Drop all MSI-X changes and the fixed MSI-X table patch (v1 patch 11), reducing the series from eleven patches to ten. - Adapt register names to the preceding DWC register-field cleanup series. Validation reported with v2: - ARM64 compilation of the Tegra driver passed. - Checkpatch and whitespace checks passed. - Tegra PCIe EP link up with pci-epf-test driver. - pci_endpoint_test - pci_ep_bar.BAR0.BAR_TEST - pci_ep_basic.CONSECUTIVE_BAR_TEST - pci_ep_basic.LEGACY_IRQ_TEST - pci_ep_basic.MSI_TEST - pci_ep_data_transfer.memcpy.READ_TEST - pci_ep_data_transfer.memcpy.WRITE_TEST - pci_ep_data_transfer.memcpy.COPY_TEST v2: https://lore.kernel.org/linux-pci/20261021061349.1265704-1-mmaddireddy@nvidia.com/ v1: https://lore.kernel.org/linux-pci/20260923072237.1139013-1-mmaddireddy@nvidia.com/ Manikanta Maddireddy (10): PCI: tegra194: Propagate REFCLK select GPIO errors PCI: tegra194: Check core reset deassertion PCI: tegra194: Fix Endpoint PERST# IRQ suspend race PCI: tegra194: Do not skip no-link Root Port remove cleanup PCI: tegra194: Check for 16 GT/s capability before programming PCI: tegra194: Check for L1SS capability before programming PCI: tegra194: Always disable Tegra234 Endpoint L1.2 PCI: tegra194: Guard Endpoint PLL-off error path PCI: tegra194: Enable core monitor clock after link setup PCI: tegra194: Reject zero MSI interrupt number drivers/pci/controller/dwc/pcie-tegra194.c | 239 +++++++++++++-------- 1 file changed, 151 insertions(+), 88 deletions(-) base-commit: d447e8cfe376cc0cc4db8266d01356d0b3ebb695 -- 2.34.1