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Mon, 2 Nov 2026 03:27:43 -0800 From: Manikanta Maddireddy To: , , , , CC: , , , , , , , , , , , , , Frank Li Subject: [PATCH v3 02/10] PCI: tegra194: Check core reset deassertion Date: Mon, 2 Nov 2026 16:57:11 +0530 Message-ID: <20261102112719.4022633-3-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261102112719.4022633-1-mmaddireddy@nvidia.com> References: <20261102112719.4022633-1-mmaddireddy@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000A88F:EE_|DS7PR12MB8249:EE_ X-MS-Office365-Filtering-Correlation-Id: dfd6b466-6d86-478d-63b3-08df38d45da6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|23010399003|36860700016|82310400026|11063799006|56012099006|261009223027099003|261028144727099003|261021123027099003|261021121427099003|261022105027099003|261026140227099003|10067099003|18002099003|22082099003|6133799003; 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If reset_control_deassert() fails, those DBI accesses can trigger a CBB timeout, or setup can return success with the core still in reset. Check core reset deassertion in Root Port setup, the DLF retry path and the Endpoint PERST# deassert path. Unwind before DBI access when deassertion fails. Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Manikanta Maddireddy Reviewed-by: Frank Li --- Changes V2 -> V3: None apart from rebasing. Changes V1 -> V2: None drivers/pci/controller/dwc/pcie-tegra194.c | 23 +++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 4490627a539a..d504d7cd3c49 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -955,6 +955,7 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci) struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); struct dw_pcie_rp *pp = &pci->pp; u32 val, offset, tmp; + int ret; bool retry = true; if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { @@ -1010,7 +1011,12 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci) appl_writel(pcie, val, APPL_CTRL); reset_control_assert(pcie->core_rst); - reset_control_deassert(pcie->core_rst); + ret = reset_control_deassert(pcie->core_rst); + if (ret) { + dev_err(pci->dev, "Failed to deassert core reset: %d\n", + ret); + return ret; + } offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF); val = dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP); @@ -1456,10 +1462,16 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK, APPL_CFG_IATU_DMA_BASE_ADDR); - reset_control_deassert(pcie->core_rst); + ret = reset_control_deassert(pcie->core_rst); + if (ret) { + dev_err(pcie->dev, "Failed to deassert core reset: %d\n", ret); + goto fail_core_rst; + } return ret; +fail_core_rst: + tegra_pcie_disable_phy(pcie); fail_phy: reset_control_assert(pcie->core_apb_rst); fail_core_apb_rst: @@ -1854,7 +1866,11 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) LTR_NOSNOOP_MSG_REQ; appl_writel(pcie, val, APPL_LTR_MSG_1); - reset_control_deassert(pcie->core_rst); + ret = reset_control_deassert(pcie->core_rst); + if (ret) { + dev_err(dev, "Failed to deassert core reset: %d\n", ret); + goto fail_core_rst; + } /* Perform cleanup that requires refclk and core reset deasserted */ pci_epc_deinit_notify(pcie->pci.ep.epc); @@ -1928,6 +1944,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) fail_init_complete: reset_control_assert(pcie->core_rst); +fail_core_rst: tegra_pcie_disable_phy(pcie); fail_phy: reset_control_assert(pcie->core_apb_rst); -- 2.34.1