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Mon, 2 Nov 2026 03:27:48 -0800 From: Manikanta Maddireddy To: , , , , CC: , , , , , , , , , , , , , Frank Li Subject: [PATCH v3 03/10] PCI: tegra194: Fix Endpoint PERST# IRQ suspend race Date: Mon, 2 Nov 2026 16:57:12 +0530 Message-ID: <20261102112719.4022633-4-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261102112719.4022633-1-mmaddireddy@nvidia.com> References: <20261102112719.4022633-1-mmaddireddy@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS8PEPF000000E3:EE_|DS0PR12MB6389:EE_ X-MS-Office365-Filtering-Correlation-Id: e233e7fd-5506-4b7a-6348-08df38d45f47 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|36860700016|1800799024|82310400026|7416014|376014|261021123027099003|261021121427099003|261022105027099003|261022075727099003|261009223027099003|261026140227099003|261026121527099003|261028144727099003|11063799006|10067099003|56012099006|18002099003|22082099003|13003099007; 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Checking ep_state before disabling the PERST# IRQ leaves a window in which PERST# deassertion starts the threaded handler after the check. The handler can enable the controller, clocks and PHYs before disable_irq() returns, but suspend still succeeds based on the earlier disabled state. The system then proceeds into suspend with an active endpoint that should have caused the suspend callback to reject the transition. Disable the PERST# IRQ before checking ep_state. disable_irq() waits for an already-running threaded handler to finish, so the state check sees its completed transition and no new handler can enable the endpoint. Re-enable the IRQ immediately if the endpoint is enabled and reject suspend. Otherwise, keep it disabled until the normal resume callback. This also balances the IRQ disable when another device aborts suspend and PM rolls back through .resume without calling .resume_early. This preserves the existing policy that PERST# is not serviced while the endpoint is suspended. It serializes the software state check with the IRQ thread; it does not make PERST# a wakeup source or guarantee delivery of transitions during suspension. Wrap the PM ops pointer with pm_sleep_ptr() so the callbacks are used only when system sleep is enabled. Fixes: c76f8eae7d46 ("PCI: tegra194: Allow system suspend when the Endpoint link is not up") Link: https://lore.kernel.org/r/20260324190755.1094879-10-mmaddireddy@nvidia.com Signed-off-by: Manikanta Maddireddy Reviewed-by: Frank Li --- Changes V2 -> V3: None apart from rebasing. Changes V1 -> V2: - Expand the commit message to explain the active-endpoint suspend race, IRQ-thread synchronization and suspend rollback handling. - Clarify that PERST# is not serviced while the endpoint is suspended. - Add a comment explaining why the IRQ thread is drained before checking endpoint state. drivers/pci/controller/dwc/pcie-tegra194.c | 34 ++++++++++++++-------- 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index d504d7cd3c49..7560422c5953 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2375,19 +2375,30 @@ static int tegra_pcie_dw_suspend(struct device *dev) { struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); - if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { - if (pcie->ep_state == EP_STATE_ENABLED) { - dev_err(dev, "Tegra PCIe is in EP mode, suspend not allowed\n"); - return -EPERM; - } - - disable_irq(pcie->pex_rst_irq); + if (pcie->of_data->mode != DW_PCIE_EP_TYPE) return 0; + + /* Drain the PERST# thread before checking whether the endpoint is idle. */ + disable_irq(pcie->pex_rst_irq); + if (pcie->ep_state == EP_STATE_ENABLED) { + enable_irq(pcie->pex_rst_irq); + dev_err(dev, "Tegra PCIe is in EP mode, suspend not allowed\n"); + return -EPERM; } return 0; } +static int tegra_pcie_dw_resume(struct device *dev) +{ + struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); + + if (pcie->of_data->mode == DW_PCIE_EP_TYPE) + enable_irq(pcie->pex_rst_irq); + + return 0; +} + static int tegra_pcie_dw_suspend_late(struct device *dev) { struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); @@ -2463,10 +2474,8 @@ static int tegra_pcie_dw_resume_early(struct device *dev) struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); u32 val; - if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { - enable_irq(pcie->pex_rst_irq); + if (pcie->of_data->mode == DW_PCIE_EP_TYPE) return 0; - } if (!pcie->link_state) return 0; @@ -2570,10 +2579,11 @@ static const struct of_device_id tegra_pcie_dw_of_match[] = { static const struct dev_pm_ops tegra_pcie_dw_pm_ops = { .suspend = tegra_pcie_dw_suspend, + .resume = tegra_pcie_dw_resume, .suspend_late = tegra_pcie_dw_suspend_late, + .resume_early = tegra_pcie_dw_resume_early, .suspend_noirq = tegra_pcie_dw_suspend_noirq, .resume_noirq = tegra_pcie_dw_resume_noirq, - .resume_early = tegra_pcie_dw_resume_early, }; static struct platform_driver tegra_pcie_dw_driver = { @@ -2582,7 +2592,7 @@ static struct platform_driver tegra_pcie_dw_driver = { .shutdown = tegra_pcie_dw_shutdown, .driver = { .name = "tegra194-pcie", - .pm = &tegra_pcie_dw_pm_ops, + .pm = pm_sleep_ptr(&tegra_pcie_dw_pm_ops), .of_match_table = tegra_pcie_dw_of_match, }, }; -- 2.34.1