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Mon, 2 Nov 2026 03:28:00 -0800 From: Manikanta Maddireddy To: , , , , CC: , , , , , , , , , , , , , Frank Li Subject: [PATCH v3 05/10] PCI: tegra194: Check for 16 GT/s capability before programming Date: Mon, 2 Nov 2026 16:57:14 +0530 Message-ID: <20261102112719.4022633-6-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261102112719.4022633-1-mmaddireddy@nvidia.com> References: <20261102112719.4022633-1-mmaddireddy@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000A893:EE_|DS7PR12MB6071:EE_ X-MS-Office365-Filtering-Correlation-Id: 30f4790c-cb31-4868-92e0-08df38d4669b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|23010399003|7416014|376014|36860700016|82310400026|11063799006|56012099006|261009223027099003|261021123027099003|261021121427099003|261022075727099003|10067099003|18002099003|22082099003|6133799003; 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If the capability is absent, the code writes lane presets at an unrelated configuration offset. Look up the capability once before the lane loop and skip the 16 GT/s lane equivalent control programming when it is absent. Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Manikanta Maddireddy Reviewed-by: Frank Li --- Changes V2 -> V3: None apart from rebasing. Changes V1 -> V2: None drivers/pci/controller/dwc/pcie-tegra194.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 0027c0adc7a1..4926fea2ee05 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -841,7 +841,11 @@ static void tegra_pcie_enable_interrupts(struct dw_pcie_rp *pp) static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie) { struct dw_pcie *pci = &pcie->pci; - u32 val, offset, i; + u32 pl16g, val, i; + + pl16g = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_PL_16GT); + if (pl16g) + pl16g += PCI_PL_16GT_LE_CTRL; /* Program init preset */ for (i = 0; i < pcie->num_lanes; i++) { @@ -852,15 +856,15 @@ static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie) GEN3_GEN4_EQ_PRESET_INIT); dw_pcie_writew_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2), val); - offset = dw_pcie_find_ext_capability(pci, - PCI_EXT_CAP_ID_PL_16GT) + - PCI_PL_16GT_LE_CTRL; - val = dw_pcie_readb_dbi(pci, offset + i); + if (!pl16g) + continue; + + val = dw_pcie_readb_dbi(pci, pl16g + i); FIELD_MODIFY(PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK, &val, GEN3_GEN4_EQ_PRESET_INIT); FIELD_MODIFY(PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK, &val, GEN3_GEN4_EQ_PRESET_INIT); - dw_pcie_writeb_dbi(pci, offset + i, val); + dw_pcie_writeb_dbi(pci, pl16g + i, val); } val = dw_pcie_readl_dbi(pci, GEN3_CTRL); -- 2.34.1