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Mon, 2 Nov 2026 03:28:18 -0800 From: Manikanta Maddireddy To: , , , , CC: , , , , , , , , , , , , , Frank Li Subject: [PATCH v3 08/10] PCI: tegra194: Guard Endpoint PLL-off error path Date: Mon, 2 Nov 2026 16:57:17 +0530 Message-ID: <20261102112719.4022633-9-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261102112719.4022633-1-mmaddireddy@nvidia.com> References: <20261102112719.4022633-1-mmaddireddy@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS8PEPF000000E0:EE_|BY5PR12MB4209:EE_ X-MS-Office365-Filtering-Correlation-Id: 21fc1c84-8b5f-4a18-7c91-08df38d46eb3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|23010399003|7416014|376014|1800799024|6133799003|10067099003|18002099003|22082099003|56012099006|11063799006|261021123027099003|261026121527099003|261026140227099003|261022105027099003|261022075727099003|261009223027099003|261028144727099003|261021121427099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Eu5FYgI/KduNpNbvLgip7doAnvHwUCJ3Kion+5/SpRESSWPtwlC8X8XvZsjX03neUi2M7I3Tt/V5ZGs/ibvp2hGGXWZIogOhMT6Cxd9faFbdsgdWMK8V3OK9OYiQ+KRaSNDwhU0ZErItnxAiuiLKjNUhGrw6y7rGiS65jkeZ7UD4tbneUrisEF1wHUiPf69mBHXwpOnURR/A1m1V87+c0T4bkCIumlUXxJ8Gf/BvO2acnE7SHa0LcEcZ1DzcC7ZQ/zhxdE5MLaGJonOseYlpfO99y524LBwrAeAMLzdmgDK670kGiwU+GbpvIMH6CYCIJTNz0ssEkRBt1wtCj0PgRlAIvo79/GEs7JE2clRB41ib/PntoJajsbwb6m0mottwvgtfeqFzQ99s+kSwughMCekQ9i/8MVnMNXt0ncRAydd/iTnec1HFQL3n5i90g37m X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Nov 2026 11:28:34.9932 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 21fc1c84-8b5f-4a18-7c91-08df38d46eb3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS8PEPF000000E0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4209 The Endpoint PERST# deassert path initializes the external-refclk PLL only when enable_ext_refclk is set, but the error unwind always sent the PLL-off request. Guard the PLL-off request with enable_ext_refclk so Tegra234 Endpoint configurations that did not enable the PLL do not send a spurious BPMP PLL-off command. Fixes: a54e19073718 ("PCI: tegra194: Add Tegra234 PCIe support") Signed-off-by: Manikanta Maddireddy Reviewed-by: Frank Li --- Changes V2 -> V3: None apart from rebasing. Changes V1 -> V2: None drivers/pci/controller/dwc/pcie-tegra194.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 0ae7adc16054..e08d99efd616 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1974,7 +1974,8 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) fail_core_apb_rst: clk_disable_unprepare(pcie->core_clk); fail_core_clk_enable: - tegra_pcie_bpmp_set_pll_state(pcie, false); + if (pcie->enable_ext_refclk) + tegra_pcie_bpmp_set_pll_state(pcie, false); fail_pll_init: tegra_pcie_bpmp_set_ctrl_state(pcie, false); fail_set_ctrl_state: -- 2.34.1