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Mon, 2 Nov 2026 04:12:21 -0800 From: Johnny Liu To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , "Prashant Gaikwad" , Stephen Boyd , Brian Masney , Jerome Brunet , "Douglas Anderson" , Aniruddha Rao , , , , CC: Johnny Liu Subject: [PATCH v3 0/4] Add Tegra238 BPMP support and fix stale EMC clock rate Date: Mon, 2 Nov 2026 12:11:58 +0000 Message-ID: <20261102121202.2431928-1-johnliu@nvidia.com> X-Mailer: git-send-email 2.43.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000026C8:EE_|SJ5PPFB332093D3:EE_ X-MS-Office365-Filtering-Correlation-Id: 39660aa0-e697-43f8-8556-08df38da990d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|36860700016|1800799024|82310400026|7416014|376014|261021123027099003|261021121427099003|261022105027099003|261009223027099003|921020|261026140227099003|261026121527099003|261028144727099003|11063799006|10067099003|56012099006|18002099003|13003099007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YNYaw7C8t6XOy0DpDEGQQyRdrwG5dbmZQDSlH731MvzYdZNCPL9Q4kjEccRuFyeqqFpgXgvCKHlZF4M0GulbUix480yMibWqpI3MMvf03RoiPdAa2g+GyaB97XWPvgb/zNa/fYFQZn7ndyFJTDIQjohD9E8oZPt3o+AwYJNrSEUlFEdN7r1q+XPP2JFeM5K4kfwqSUWi3qZl20o4YMz1XSBKWKpKjNJav3tH7MDRogCohnOmt2Rnya+9IkQMb2CRZsEzKd1E9EmU4wdA0XsmRDlRoq6gGrVGnNdrqjaKI72GTJga5eQEeoGUvB65qmJy50GIv4KpFa9EVOS/Qwz4LL41DkpZHVeChdLZoiwXJRlrg13iNsWPxQ6fMeRc4nWYfAnr33DiUPqH5finFen+yHa2zQtD7zsDhTRykCYbRQrskf9J2D/cAm6e/OgszzeT X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Nov 2026 12:12:43.1394 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39660aa0-e697-43f8-8556-08df38da990d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000026C8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPFB332093D3 EMC clock scaling is handled by the BPMP firmware without kernel involvement, so clk_get_rate() on the EMC clock can return a stale value cached by the common clock framework. This series makes the EMC clock rate uncached on Tegra234, Tegra238 and Tegra264, and adds the pieces needed to identify the EMC clock on each of these chips. The EMC clock ID differs per chip (TEGRA234_CLK_EMC=31, TEGRA238_CLK_EMC=43, TEGRA264_CLK_EMC=290), while the "nvidia,tegra186-bpmp" fallback compatible and the tegra186_soc data are shared across several chips. To avoid detecting the chip at runtime, the EMC clock ID is carried in per-SoC BPMP data selected by the device tree compatible. Patch 1 adds the "nvidia,tegra238-bpmp" compatible to the binding, together with the Tegra238 clock ID header. Patch 2 adds an emc_clk_id field to struct tegra_bpmp_soc, together with dedicated SoC data for Tegra234 and Tegra264 built on a common TEGRA186_BPMP_SOC_COMMON initializer. Patch 3 adds Tegra238 support to the BPMP driver, including its own SoC data and EMC clock ID. Patch 4 then sets CLK_GET_RATE_NOCACHE on the clock matching that ID, so that the common clock framework forwards rate queries to the BPMP instead of returning a stale cached rate. The series touches both the clock and the firmware code. Patch 4 depends on patch 2, and patch 3 depends on patches 1 and 2, so I would suggest taking the whole series through the Tegra tree with an Acked-by from the clock maintainers. Changes in v3: - Move the TEGRA186_BPMP_SOC_COMMON refactoring out of the Tegra238 support patch and into the "Add per-SoC EMC clock ID" patch, as the refactoring only makes sense together with the per-SoC emc_clk_id. - Keep all Tegra238 specific changes (Makefile, CONFIG_ARCH_TEGRA_238_SOC guards, clock ID header include, tegra238_soc data and compatible match) in a single "Add Tegra238 support" patch, and reorder it after the per-SoC EMC clock ID patch. - Reword the "Add per-SoC EMC clock ID" commit message to describe the intended use of emc_clk_id: the BPMP clock provider sets CLK_GET_RATE_NOCACHE on that clock, as it is completely managed by the firmware and the common clock framework must pass rate queries through to get the latest rate. - No changes to patches 1 and 4 apart from the patch numbering. Changes in v2: - Squash "dt-bindings: clock: Add Tegra238 BPMP clock IDs" into "dt-bindings: firmware: tegra186-bpmp: Add Tegra238 compatible". - Reword the binding commit message to state that the Tegra238 SoC is fully compatible with the Tegra186 BPMP. v2: https://lore.kernel.org/all/20261028155000.1205739-1-johnliu@nvidia.com/ v1: https://lore.kernel.org/all/20261028084900.1047287-1-johnliu@nvidia.com/ Johnny Liu (4): dt-bindings: firmware: tegra186-bpmp: Add Tegra238 BPMP firmware: tegra: bpmp: Add per-SoC EMC clock ID firmware: tegra: bpmp: Add Tegra238 support clk: tegra: bpmp: Do not cache the EMC clock rate .../firmware/nvidia,tegra186-bpmp.yaml | 1 + drivers/clk/tegra/clk-bpmp.c | 3 + drivers/firmware/tegra/Makefile | 1 + drivers/firmware/tegra/bpmp.c | 61 ++-- include/dt-bindings/clock/nvidia,tegra238.h | 279 ++++++++++++++++++ include/soc/tegra/bpmp.h | 1 + 6 files changed, 329 insertions(+), 17 deletions(-) create mode 100644 include/dt-bindings/clock/nvidia,tegra238.h -- 2.43.0