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Mon, 2 Nov 2026 04:12:23 -0800 From: Johnny Liu To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , "Prashant Gaikwad" , Stephen Boyd , Brian Masney , Jerome Brunet , "Douglas Anderson" , Aniruddha Rao , , , , CC: Johnny Liu Subject: [PATCH v3 2/4] firmware: tegra: bpmp: Add per-SoC EMC clock ID Date: Mon, 2 Nov 2026 12:12:00 +0000 Message-ID: <20261102121202.2431928-3-johnliu@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261102121202.2431928-1-johnliu@nvidia.com> References: <20261102121202.2431928-1-johnliu@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY6PEPF0000004E:EE_|PH7PR12MB6444:EE_ X-MS-Office365-Filtering-Correlation-Id: a16fe91c-0012-42fe-bf4d-08df38da9977 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|7416014|1800799024|82310400026|36860700016|921020|261021123027099003|261021121427099003|11063799006|56012099006|261009223027099003|10067099003|22082099003|18002099003|6133799003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: C6XenhkU0kFSGhmfFyfQoyvmq6SLzGTmSVrdJuZVOPWkcKiqBefQxjSMbz2I7OUaMtM5dBSiX50nOffQu5Vb7Xj/xAa1rfWlizrTLcHesq00oNS840EUscnHFtoHRaq+Rvw570MP++QRvXs7uSuA02izXTptp6B3DghmnoubWTgsg9YYm7PuMTLMwsUrDLz3TTx0iUdd4GL+jit28Ua5fzU5Lx8qNXj2DXX3IsXAppcb2P447Ag70t1Tzktgnxp4h8WJeCQyNHqnkWGjDPFdE/Rhs45mBrFRaWhk2wvcWnK4bhijLlWndoc/3DSb4F85qqSe4efA2Aj52N5jCYTMIHzTRPDLZJbzF7+t3qHVgbqoOXolNHZ0x4TrLy/04bxN4Qipeiy70X1ZCt1EhABrDYMACpB4W6tDbgssbEYoeA55ajlpeHMjM7qzObNkNMvE X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Nov 2026 12:12:43.7505 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a16fe91c-0012-42fe-bf4d-08df38da9977 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY6PEPF0000004E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6444 The EMC clock ID differs per chip (TEGRA234_CLK_EMC=31, TEGRA264_CLK_EMC=290). Add an emc_clk_id field to struct tegra_bpmp_soc and set it for Tegra234 and Tegra264. The specified EMC clock ID is intended to be used by the BPMP common clock provider driver to set the CLK_GET_RATE_NOCACHE flag on that clock. Since the EMC clock is completely managed by the firmware, the common clock framework must not read back a stale cached rate, but forcefully pass the request through to the firmware to get the latest clock rate. To describe such chip specific properties, give Tegra234 and Tegra264 dedicated SoC data selected through their specific compatibles, built on top of a common TEGRA186_BPMP_SOC_COMMON initializer. Tegra186 and Tegra194 keep using tegra186_soc. Signed-off-by: Johnny Liu --- drivers/firmware/tegra/bpmp.c | 52 +++++++++++++++++++++++------------ include/soc/tegra/bpmp.h | 1 + 2 files changed, 36 insertions(+), 17 deletions(-) diff --git a/drivers/firmware/tegra/bpmp.c b/drivers/firmware/tegra/bpmp.c index d3508e98e338..5d97a8600fd1 100644 --- a/drivers/firmware/tegra/bpmp.c +++ b/drivers/firmware/tegra/bpmp.c @@ -21,6 +21,9 @@ #include #include +#include +#include + #include "bpmp-private.h" #define MSG_ACK BIT(0) @@ -1132,24 +1135,37 @@ static const struct dev_pm_ops tegra_bpmp_pm_ops = { IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \ IS_ENABLED(CONFIG_ARCH_TEGRA_264_SOC) +#define TEGRA186_BPMP_SOC_COMMON \ + .channels = { \ + .cpu_tx = { \ + .offset = 3, \ + .timeout = 60 * USEC_PER_SEC, \ + }, \ + .thread = { \ + .offset = 0, \ + .count = 3, \ + .timeout = 600 * USEC_PER_SEC, \ + }, \ + .cpu_rx = { \ + .offset = 13, \ + .timeout = 0, \ + }, \ + }, \ + .ops = &tegra186_bpmp_ops, \ + .num_resets = 193 + static const struct tegra_bpmp_soc tegra186_soc = { - .channels = { - .cpu_tx = { - .offset = 3, - .timeout = 60 * USEC_PER_SEC, - }, - .thread = { - .offset = 0, - .count = 3, - .timeout = 600 * USEC_PER_SEC, - }, - .cpu_rx = { - .offset = 13, - .timeout = 0, - }, - }, - .ops = &tegra186_bpmp_ops, - .num_resets = 193, + TEGRA186_BPMP_SOC_COMMON, +}; + +static const struct tegra_bpmp_soc tegra234_soc = { + TEGRA186_BPMP_SOC_COMMON, + .emc_clk_id = TEGRA234_CLK_EMC, +}; + +static const struct tegra_bpmp_soc tegra264_soc = { + TEGRA186_BPMP_SOC_COMMON, + .emc_clk_id = TEGRA264_CLK_EMC, }; #endif @@ -1182,6 +1198,8 @@ static const struct of_device_id tegra_bpmp_match[] = { IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \ IS_ENABLED(CONFIG_ARCH_TEGRA_264_SOC) { .compatible = "nvidia,tegra186-bpmp", .data = &tegra186_soc }, + { .compatible = "nvidia,tegra234-bpmp", .data = &tegra234_soc }, + { .compatible = "nvidia,tegra264-bpmp", .data = &tegra264_soc }, #endif #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) { .compatible = "nvidia,tegra210-bpmp", .data = &tegra210_soc }, diff --git a/include/soc/tegra/bpmp.h b/include/soc/tegra/bpmp.h index f55db918ccb1..40e2db8e69cc 100644 --- a/include/soc/tegra/bpmp.h +++ b/include/soc/tegra/bpmp.h @@ -31,6 +31,7 @@ struct tegra_bpmp_soc { const struct tegra_bpmp_ops *ops; const struct tegra_bpmp_mbwt_soc *mbwt; unsigned int num_resets; + unsigned int emc_clk_id; }; struct tegra_bpmp_mb_data { -- 2.43.0