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Mon, 02 Nov 2026 06:24:55 -0800 (PST) Received: from localhost ([2.27.148.106]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2eb39298543sm28720445ad.60.2026.11.02.06.24.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2026 06:24:54 -0800 (PST) From: Han Gao To: Philipp Zabel Cc: Han Gao , gaohan@iscas.ac.cn, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Zhiguo Zhu , Stephen Boyd , Brian Masney , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Thomas Gleixner , Radu Rendec , Samuel Holland , Daniel Lezcano , Anup Patel , Icenowy Zheng , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Paul Walmsley Subject: Re: [PATCH 14/18] riscv: dts: zhihe: add A210 UARTs Date: Mon, 2 Nov 2026 22:24:46 +0800 Message-ID: <20261102142448.3784989-1-rabenda.cn@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: References: X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On Thu, 22 Oct 2026 11:22:51 +0200 Philipp Zabel wrote: > On Do, 2026-10-22 at 03:53 +0800, Han Gao via B4 Relay wrote: > > From: Zhiguo Zhu > > > > Add the ten A210 UARTs with their clocks, resets and interrupts, using > > the snps,dw-apb-uart compatible. > > > > Signed-off-by: Zhiguo Zhu > > Co-developed-by: Han Gao > > Signed-off-by: Han Gao > > --- > > arch/riscv/boot/dts/zhihe/a210.dtsi | 150 ++++++++++++++++++++++++++++++++++++ > > 1 file changed, 150 insertions(+) > > > > diff --git a/arch/riscv/boot/dts/zhihe/a210.dtsi b/arch/riscv/boot/dts/zhihe/a210.dtsi > > index bbad51a3edb0..a07b67d10633 100644 > > --- a/arch/riscv/boot/dts/zhihe/a210.dtsi > > +++ b/arch/riscv/boot/dts/zhihe/a210.dtsi > > @@ -405,6 +405,66 @@ rst_peri1: reset-controller@2010400 { > > #reset-cells = <1>; > > }; > > > > + uart0: serial@2014000 { > > + compatible = "snps,dw-apb-uart"; > > Prepend a vendor compatible if you need two resets, similar to > "starfive,jh7100-uart"? Thanks, agreed. The RFC that replaced this series adds a "zhihe,a210-uart" compatible and lists both resets. > > > + reg = <0x0 0x02014000 0x0 0x400>; > > + clocks = <&clk_peri PERI1_UART0_SCLK_EN>, > > + <&clk_peri PERI1_UART0_PCLK_EN>; > > + clock-names = "baudclk", "apb_pclk"; > > + interrupt-parent = <&intc>; > > + interrupts = <321 IRQ_TYPE_LEVEL_HIGH>; > > + reg-io-width = <4>; > > + reg-shift = <2>; > > + resets = <&rst_peri1 PERI1_UART0_PRST>; > > This looks to me like it should be > > resets = <&rst_peri1 PERI1_UART0_PRST>, > <&rst_peri1 PERI1_UART0_S_RST>; > > instead. > > regards > Philipp > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv Sent using hkml (https://github.com/sjp38/hackermail)