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Mon, 02 Nov 2026 06:30:18 -0800 (PST) Received: from localhost ([2.27.148.106]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8aad77fcb8dsm2219095b3a.1.2026.11.02.06.30.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2026 06:30:17 -0800 (PST) From: Han Gao To: Conor Dooley Cc: Han Gao , gaohan@iscas.ac.cn, Drew Fustini , Paul Walmsley , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, Rob Herring , Jerome Brunet , Alexandre Ghiti , Anup Patel , Radu Rendec , Zhiguo Zhu , devicetree@vger.kernel.org, Conor Dooley , Albert Ou , Bartosz Golaszewski , linux-gpio@vger.kernel.org, Daniel Lezcano , Brian Masney , Krzysztof Kozlowski , Stephen Boyd , Linus Walleij , linux-kernel@vger.kernel.org, Samuel Holland , Palmer Dabbelt , Thomas Gleixner , Philipp Zabel , Paul Walmsley Subject: Re: [PATCH 13/18] riscv: dts: zhihe: add A210 core support Date: Mon, 2 Nov 2026 22:30:09 +0800 Message-ID: <20261102143010.3785824-1-rabenda.cn@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261022-radiation-ivory-c8f9f9c66b7f@spud> References: X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On Thu, 22 Oct 2026 19:48:36 +0100 Conor Dooley wrote: > On Thu, Oct 22, 2026 at 03:53:33AM +0800, Han Gao via B4 Relay wrote: > > + soc { > > + compatible = "simple-bus"; > > + ranges; > > + #address-cells = <2>; > > + dma-noncoherent; > > + #size-cells = <2>; > > + > > + clk: clock-controller@260000 { > > + compatible = "zhihe,a210-clk"; > > + reg = <0x0 0x00260000 0x0 0x1000>, > > + <0x0 0x00250000 0x0 0x1000>, > > + <0x0 0x10141600 0x0 0x100>, > > + <0x0 0x10141400 0x0 0x100>, > > + <0x0 0x04810000 0x0 0x1000>, > > + <0x0 0x05810000 0x0 0x1000>, > > + <0x0 0x04900000 0x0 0x1000>, > > + <0x0 0x20250000 0x0 0x1000>, > > + <0x0 0x10140000 0x0 0xe00>; > > This looks very much like an incorrect modelling of the device. > Most of these should be individual devices, and those labeled "sysreg" > probably should be syscons as they likely contain multiple functions, > not just clocks? > > > + reg-names = "pll-wrap", "top-crg", "cpu-ss-clk-sysreg", > > + "cpu-ss-cpu-pll", "ddr0-sysreg", > > + "ddr1-sysreg", "slc-dual-sysreg", > > + "top-crg-t", "cpu-ss-ccu"; > > + #clock-cells = <1>; > > + clocks = <&osc_32k>, <&osc_24m>, <&rc_24m>; > > + clock-names = "osc-32k", "osc-24m", "rc-24m"; > > + }; > > + > > + clk_peri: clock-controller@300200 { > > + compatible = "zhihe,a210-peri-clk"; > > + reg = <0x0 0x00300200 0x0 0x4>, > > + <0x0 0x02010200 0x0 0x8>, > > + <0x0 0x08400200 0x0 0x8>, > > + <0x0 0x00540200 0x0 0x4>, > > + <0x0 0x27420200 0x0 0x200>; > > Same here, particularly things that are only a single word wide... > > > + reg-names = "peri0-sysreg", "peri1-sysreg", > > + "peri2-sysreg", "peri3-sysreg", "tee-crg"; > > + #clock-cells = <1>; > > + }; > > > + clk_aon: clock-controller@30844000 { > > + compatible = "zhihe,a210-aon-clk"; > > + reg = <0 0x30844000 0 0x1c>; > > 0x1c is also suspiciously narrow, but believable. Is there a register > map for this device available somewhere (ideally in english, but I > suppose machine translation will do a sufficient job) so that I can try > to understand how this device should be modelled? Thanks. There is no public register map, unfortunately. In the next version the E902 firmware will take over these blocks, and Linux will get clocks and resets through SCMI instead, so they will no longer be described in the DT. > > Thanks, > Conor. > > > + #clock-cells = <1>; > > + clocks = <&aon_110m>, <&osc_24m>, <&aon_rc>, <&osc_32k>; > > + clock-names = "high", "osc", "rc", "rtc"; > > + }; > Sent using hkml (https://github.com/sjp38/hackermail)