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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cdb364a04b8sm358654a12.21.2026.11.02.14.05.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2026 14:05:05 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Nico Angelo Dela Cruz , Rob Clark , Konrad Dybcio , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 13/15] drm/msm/a8xx: Use CP_PROTECT_PIPE regs Date: Mon, 2 Nov 2026 14:02:57 -0800 Message-ID: <20261102220405.30730-14-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261102220405.30730-1-robin.clark@oss.qualcomm.com> References: <20261102220405.30730-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=SeZi5fRu c=1 sm=1 tr=0 ts=6ae90913 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=Dhg23qV5XRRJQlZlKu4A:9 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTAyMDA4NyBTYWx0ZWRfXyjLz5MZMttzE fby/gUNyv3MxLaj9a23qW5dzGfrxy2uKUBBq60i42nadZSy2T3VXtxCam4+lekbhoaZwbT9UtzH o+hrSUoBxmkV+X22i54WmY/pksL0wiRbFWReJAOXvq8pK7XJqFvif0nWpUcDm2G8MRQHNtFpAWp e/eM8y4++1Mf6U2cDo7Fvq6JOdz9Q0N03giS872uz6kgy2dR3a6KS1AM+pXz9tgkC1pd++74dZS 36zVU0LNWGsXTJwrfU4zBWisfi7SFktO5r7Ynw0wU39PT+EHo6pfXqM9gvvc9A5oytn/IFATHpW w1zVS8UNVufbcexBn9c7leJ2OX5zYP6Xv1YoCkeNry8mIZrzyiRGM/V4ykGQXDTWpcrD/+IDMi6 uemIB3jZc/s4xMoCMIh2yg0b+uL+oaljsC+SelGX8JMRpOuuDMHoLteArTc8iGg/kyV9KHaI450 XlmLIF9LdqnaGEzqefw== X-Proofpoint-Spam-Info: AW1haW4tMjYxMTAyMDA4NyBTYWx0ZWRfX8EkStk4gMp09 L23sJ1zWluyuPILBnhDXqw8bH0S2z3cnTkFfIRQ3wFXfIc6lLSLZn77CphsxABFKnHGZ+wf7YUt iOAmBoKl5na40ylSFGKeido9epjGiH8= X-Proofpoint-ORIG-GUID: etby_N4l_LE0MTZK-uPJw47bandjygGM X-Proofpoint-GUID: etby_N4l_LE0MTZK-uPJw47bandjygGM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-02_06,2026-11-02_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611020087 If there are not enough global CP_PROTECT_GLOBAL regs, we can use CP_PROTECT_PIPE regs for the extra spans. We just need to configure them the same on all pipes. Tested-by: Alexander Koskovich # Milos (Nothing Phone 3a) Reviewed-by: Konrad Dybcio Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index 952c46f08d2a..0dd8444cde22 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -258,12 +258,21 @@ static void a8xx_set_cp_protect(struct msm_gpu *gpu) a8xx_aperture_clear(gpu); - for (i = 0; i < protect->count; i++) { + for (i = 0; i < min(64, protect->count); i++) { /* Intentionally skip writing to some registers */ - if (protect->regs[i]) { - gpu_write(gpu, REG_A8XX_CP_PROTECT_GLOBAL(i), protect->regs[i]); - final_cfg = protect->regs[i]; - } + if (!protect->regs[i]) + continue; + gpu_write(gpu, REG_A8XX_CP_PROTECT_GLOBAL(i), protect->regs[i]); + final_cfg = protect->regs[i]; + } + + for (; i < protect->count; i++) { + /* Intentionally skip writing to some registers */ + if (!protect->regs[i]) + continue; + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(i - 64), protect->regs[i]); + a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(i - 64), protect->regs[i]); + final_cfg = protect->regs[i]; } /* -- 2.56.0