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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2eb3928104asm32390475ad.53.2026.11.02.14.04.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2026 14:04:30 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Nico Angelo Dela Cruz , Rob Clark , Konrad Dybcio , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 06/15] drm/msm/a8xx: Allow nonctx reglist to include GMU regs Date: Mon, 2 Nov 2026 14:02:50 -0800 Message-ID: <20261102220405.30730-7-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261102220405.30730-1-robin.clark@oss.qualcomm.com> References: <20261102220405.30730-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTAyMDA4NyBTYWx0ZWRfX/UGTM5r7YmMy V9Vqf0zBUlyHYXnp9pAzNsn7Uai/URYtF8QtnSdPp6Rc+QB8a19M52717g4trYyQMw7N2cBeyhN YLNNXLQAwaaabiPZ/9LsPZvsaue5+/LEaiG+jA2088r4NBqTaTPNgtziHSV2DCUwh7DrBRVtRoD AsPgZ1Y233xyUvkNVJbtJ4FkzDBfRmriarvgBH7GdyL2UE8wDb0UubwZzgR7uaSl4/3wPiNrw/+ qw2m98LmOjkDDxFqyOABLZGYWnxHEE4WqbLAoosEMcrJXzbqF2ifc2ZbC/wRZKR8gEzrUtCDZ9G vrtWsXz6ZuKCkA/Or0lTG9iEHEOMlhwtmuw3D/CshZwrUPfbiL1Qq39h1ZhX//A7OMvJ7ljotMB bNFJ0U3ciYD16OrHFgCYwTlvcCpq4MtKyeWezhm1WOfjSKKRsLELagSitkyva3UJhehZc6QJVcc FIO7xFzRmHHcxWiIKAw== X-Proofpoint-ORIG-GUID: Sle2Pxx-gwNmbU3Ag5_W8iNNi-_p8pB3 X-Proofpoint-GUID: Sle2Pxx-gwNmbU3Ag5_W8iNNi-_p8pB3 X-Authority-Analysis: v=2.4 cv=B/wsQ+tM c=1 sm=1 tr=0 ts=6ae908f0 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=cg0wMmP-TNBUvudz7-YA:9 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTAyMDA4NyBTYWx0ZWRfX5DO/P6z8J7gR nm2wpBY6rQSdMN4VPJKN6rc4+aL/hvx/+w6WIfQSZQQXQLTVv+pqkhp3S+Slh2yiDYfeMINTD7m PApnJN9M1M+Xgy9cGAp0pKc5KSdZ75U= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-02_06,2026-11-02_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 suspectscore=0 adultscore=0 clxscore=1015 impostorscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611020087 >From hw PoV, it's all part of the GPU. But from dt perspective it is it's own device with a separate io space. So we need to detect this and direct writes to the correct place. Acked-by: Konrad Dybcio Tested-by: Alexander Koskovich # Milos (Nothing Phone 3a) Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index 6b299bf1000f..59546fc636cd 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -370,6 +370,7 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu) static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gmu *gmu = &to_a6xx_gpu(adreno_gpu)->gmu; const struct a6xx_info *info = adreno_gpu->info->a6xx; const struct adreno_reglist_pipe *regs = info->nonctxt_reglist; unsigned int pipe_id, i; @@ -389,7 +390,11 @@ static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) if (regs[i].offset == REG_A8XX_RB_GC_GMEM_PROTECT) *gmem_protect = regs[i].value; - gpu_write(gpu, regs[i].offset, regs[i].value); + if ((regs[i].offset << 2) >= gmu->mmio_offset) { + gmu_write(gmu, regs[i].offset, regs[i].value); + } else { + gpu_write(gpu, regs[i].offset, regs[i].value); + } } a8xx_aperture_release(gpu, flags); -- 2.56.0