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Mon, 02 Nov 2026 14:04:50 -0800 (PST) Received: from DESKTOP-NM9EKIA ([125.134.240.130]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36a429467cdsm38466358eec.19.2026.11.02.14.04.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2026 14:04:50 -0800 (PST) From: Joonhoe Kim <26rote@gmail.com> To: Konrad Dybcio , vkoul@kernel.org Cc: neil.armstrong@linaro.org, mani@kernel.org, dmitry.baryshkov@oss.qualcomm.com, val@packett.cool, wesley.cheng@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] phy: qcom: qmp-combo: Leave the USB PCS alone in DP-only mode Date: Tue, 3 Nov 2026 07:04:50 +0900 Message-ID: <20261102220450.1670-1-26rote@gmail.com> X-Mailer: git-send-email 2.55.0.windows.5 In-Reply-To: <4d831e77-2123-46eb-90ed-dca3c580d47e@oss.qualcomm.com> References: <20261023123512.1912-1-26rote@gmail.com> <4d831e77-2123-46eb-90ed-dca3c580d47e@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 11/2/26 10:32 PM, Konrad Dybcio wrote: > On 10/23/26 2:35 PM, Joonhoe Kim wrote: [...] >> - ret = qmp_combo_usb_power_on(phy); >> - if (ret) { >> - qmp_combo_com_exit(qmp, false); >> - return ret; >> + if (qmp->qmpphy_mode != QMPPHY_MODE_DP_ONLY) { >> + ret = qmp_combo_usb_power_on(phy); [...] > The USB sub-block provides the PIPE clock to the DWC3 controller. > If we somehow enter DP altmode before DWC3 gets to probe, or if for > any reason we need to access that controller (maybe debugfs reads), > I think this will fail. Right, there is no PIPE clock then. But there is none without this patch either. In DP-only mode, qmp_combo_usb_power_on() writes the USB tables over the lanes DP is using. Here it timed out waiting for PHYSTATUS when resuming in that mode, so phy_init() fails. DP-only mode is usually entered after DWC3 has probed. The mux then powers the USB PCS down under the running controller. So accessing the controller in that state already has no PIPE clock today. With this patch, the probe-after-DP case ends up in the same state instead of failing in phy_init(). The missing PIPE clock does break things on Kaanapali: starting the host in DP-only mode fails ("Host halt failed, -110"). I've sent a dwc3-qcom series for this [1]. It switches the controller to the UTMI clock in DP-only modes, like "qcom,select-utmi-as-pipe-clk" does statically. It also makes the controller a mode switch, so pmic_glink_altmode cannot set the mux before dwc3-qcom has probed. [1] https://lore.kernel.org/all/20261102215121.738-1-26rote@gmail.com/ Thanks, Joonhoe Kim