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Mon, 02 Nov 2026 14:05:04 -0800 (PST) Received: from DESKTOP-NM9EKIA ([125.134.240.130]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36a42952e1csm43006249eec.20.2026.11.02.14.04.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2026 14:05:03 -0800 (PST) From: Joonhoe Kim <26rote@gmail.com> To: Konrad Dybcio Cc: Dmitry Baryshkov , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Antonino Maniscalco , Kalyan Thota , Federico Amedeo Izzo , Helen Koike , Vignesh Raman , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 09/10] drm/msm/dpu: only reassign resources when the encoder is reprogrammed Date: Tue, 3 Nov 2026 07:05:01 +0900 Message-ID: <20261102220501.1704-1-26rote@gmail.com> X-Mailer: git-send-email 2.55.0.windows.5 In-Reply-To: <86bf919b-5528-42bb-aa89-b518452ed7a0@oss.qualcomm.com> References: <20261024-fd-kms-fix-smmu-v5-0-a5b0b284aead@oss.qualcomm.com> <20261024-fd-kms-fix-smmu-v5-9-a5b0b284aead@oss.qualcomm.com> <86bf919b-5528-42bb-aa89-b518452ed7a0@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 10/26/26 10:19 AM, Konrad Dybcio wrote: > LLM is curious whether turning off CTM/GAMMA should trigger a modeset too. > My hunch is "yes" Some data for that. I tested 7/10 and this patch on v7.3, on a Lenovo Y700 Gen 5 (TB323FU, Kaanapali, bonded DSI) with out-of-tree board support. I counted msm_dsi_host_power_off/on with kprobes. - A compositor faded a night light filter in and out twice through the legacy CTM property. These are blob -> blob updates only. No modesets, no visible blink. - With no compositor running, a small client set the CTM through the legacy property ioctl: two rounds of NULL -> A -> B -> A -> NULL. No modesets. The CRTC kept its DSPPs after each A -> NULL. So turning the CTM off does not release the DSPPs. On chips with a single DSPP, another CRTC asking for a CTM would then fail dpu_rm_reserve(), as I noted on v4. This run does not cover the first NULL -> blob on a CRTC without DSPPs. As with v4, the tree carries out-of-tree SPR (sub-pixel rendering) support. For the test, dpu_crtc_needs_dspp() also returned true when SPR is enabled. Tested-by: Joonhoe Kim <26rote@gmail.com> # Kaanapali Thanks, Joonhoe Kim