From: Michael Gur <michaelgur@nvidia.com>
To: jgg@ziepe.ca, leon@kernel.org, linux-rdma@vger.kernel.org
Cc: Edward Srouji <edwards@nvidia.com>,
Yishai Hadas <yishaih@nvidia.com>,
Michael Gur <michaelgur@nvidia.com>,
Jason Gunthorpe <jgg@nvidia.com>,
Saeed Mahameed <saeedm@nvidia.com>,
Tariq Toukan <tariqt@nvidia.com>, Mark Bloch <mbloch@nvidia.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@kernel.org>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
linux-kernel@vger.kernel.org (open list),
netdev@vger.kernel.org (open list:MELLANOX MLX5 core VPI driver)
Subject: [PATCH rdma-next v2 07/15] mlx5: Consolidate mkey ordering setting into a single core helper
Date: Tue, 3 Nov 2026 00:33:00 +0200 [thread overview]
Message-ID: <20261102223325.2115128-8-michaelgur@nvidia.com> (raw)
In-Reply-To: <20261102223325.2115128-1-michaelgur@nvidia.com>
Consolidate the mkey ordering setting of all mlx5 consumers into a
single exported core helper. The helper takes the requested ordering
level (strict, relaxed or unordered) and sets the mkey ordering fields
according to the device caps, so consumers no longer open-code the cap
checks. The unordered level is used later in this series.
Switch the RDMA MR creation and UMR access-modify paths to the helper.
As before, strict ordering leaves the mkey context untouched.
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Yishai Hadas <yishaih@nvidia.com>
Signed-off-by: Michael Gur <michaelgur@nvidia.com>
---
drivers/infiniband/hw/mlx5/mlx5_ib.h | 7 ++++
drivers/infiniband/hw/mlx5/mr.c | 12 ++-----
drivers/infiniband/hw/mlx5/umr.c | 10 ++----
drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 -
.../ethernet/mellanox/mlx5/core/en_common.c | 13 +-------
.../net/ethernet/mellanox/mlx5/core/en_main.c | 4 +--
drivers/net/ethernet/mellanox/mlx5/core/mr.c | 32 +++++++++++++++++++
include/linux/mlx5/driver.h | 8 +++++
8 files changed, 55 insertions(+), 32 deletions(-)
diff --git a/drivers/infiniband/hw/mlx5/mlx5_ib.h b/drivers/infiniband/hw/mlx5/mlx5_ib.h
index 86465d9d2b5a..dd1fe8fd4220 100644
--- a/drivers/infiniband/hw/mlx5/mlx5_ib.h
+++ b/drivers/infiniband/hw/mlx5/mlx5_ib.h
@@ -1675,6 +1675,13 @@ static inline bool mlx5_umem_needs_ats(struct mlx5_ib_dev *dev,
return access_flags & IB_ACCESS_RELAXED_ORDERING;
}
+static inline enum mlx5_mkey_order mlx5r_access_to_mkey_order(int access_flags)
+{
+ if (access_flags & IB_ACCESS_RELAXED_ORDERING)
+ return MLX5_MKEY_ORDER_RELAXED;
+ return MLX5_MKEY_ORDER_STRICT;
+}
+
int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num,
unsigned int index, const union ib_gid *gid,
const struct ib_gid_attr *attr);
diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c
index a15610c6211c..6f57dfc7f4cd 100644
--- a/drivers/infiniband/hw/mlx5/mr.c
+++ b/drivers/infiniband/hw/mlx5/mr.c
@@ -70,16 +70,8 @@ static void set_mkc_access_pd_addr_fields(void *mkc, int acc, u64 start_addr,
MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE));
MLX5_SET(mkc, mkc, lr, 1);
- if (acc & IB_ACCESS_RELAXED_ORDERING) {
- if (MLX5_CAP_GEN(dev->mdev, mkc_order_write_after_write_ro))
- MLX5_SET(mkc, mkc, order_write_after_write, 1);
-
- if (MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read) ||
- (MLX5_CAP_GEN(dev->mdev,
- relaxed_ordering_read_pci_enabled) &&
- pcie_relaxed_ordering_enabled(dev->mdev->pdev)))
- MLX5_SET(mkc, mkc, pci_relaxed_ordered_read, 1);
- }
+ mlx5_core_mkey_set_ordering(dev->mdev, mkc,
+ mlx5r_access_to_mkey_order(acc));
MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
MLX5_SET(mkc, mkc, qpn, 0xffffff);
diff --git a/drivers/infiniband/hw/mlx5/umr.c b/drivers/infiniband/hw/mlx5/umr.c
index 144cf851c41e..2f3147c7f78f 100644
--- a/drivers/infiniband/hw/mlx5/umr.c
+++ b/drivers/infiniband/hw/mlx5/umr.c
@@ -445,18 +445,14 @@ static void mlx5r_umr_set_access_flags(struct mlx5_ib_dev *dev,
struct mlx5_mkey_seg *seg,
unsigned int access_flags)
{
- bool ro_read = (access_flags & IB_ACCESS_RELAXED_ORDERING) &&
- (MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read) ||
- pcie_relaxed_ordering_enabled(dev->mdev->pdev));
-
MLX5_SET(mkc, seg, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
MLX5_SET(mkc, seg, rw, !!(access_flags & IB_ACCESS_REMOTE_WRITE));
MLX5_SET(mkc, seg, rr, !!(access_flags & IB_ACCESS_REMOTE_READ));
MLX5_SET(mkc, seg, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE));
MLX5_SET(mkc, seg, lr, 1);
- MLX5_SET(mkc, seg, order_write_after_write,
- !!(access_flags & IB_ACCESS_RELAXED_ORDERING));
- MLX5_SET(mkc, seg, pci_relaxed_ordered_read, ro_read);
+
+ mlx5_core_mkey_set_ordering(dev->mdev, seg,
+ mlx5r_access_to_mkey_order(access_flags));
}
int mlx5r_umr_rereg_pd_access(struct mlx5_ib_mr *mr, struct ib_pd *pd,
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h
index a3945195f454..eea4844d7645 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h
@@ -1203,7 +1203,6 @@ int mlx5e_modify_tirs_lb(struct mlx5_core_dev *mdev, bool enable_uc_lb,
bool enable_mc_lb);
int mlx5e_refresh_tirs(struct mlx5_core_dev *mdev, bool enable_uc_lb,
bool enable_mc_lb);
-void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);
/* common netdev helpers */
void mlx5e_create_q_counters(struct mlx5e_priv *priv);
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c b/drivers/net/ethernet/mellanox/mlx5/core/en_common.c
index 2dbcf6673916..f01340998f52 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_common.c
@@ -38,17 +38,6 @@
* Global resources are common to all the netdevices created on the same nic.
*/
-void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc)
-{
- bool ro_write = MLX5_CAP_GEN(mdev, mkc_order_write_after_write_ro);
- bool ro_read = MLX5_CAP_GEN(mdev, pci_relaxed_ordered_read) ||
- (pcie_relaxed_ordering_enabled(mdev->pdev) &&
- MLX5_CAP_GEN(mdev, relaxed_ordering_read_pci_enabled));
-
- MLX5_SET(mkc, mkc, pci_relaxed_ordered_read, ro_read);
- MLX5_SET(mkc, mkc, order_write_after_write, ro_write);
-}
-
int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey)
{
int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
@@ -64,7 +53,7 @@ int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey)
MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA);
MLX5_SET(mkc, mkc, lw, 1);
MLX5_SET(mkc, mkc, lr, 1);
- mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
+ mlx5_core_mkey_set_ordering(mdev, mkc, MLX5_MKEY_ORDER_RELAXED);
MLX5_SET(mkc, mkc, pd, pdn);
MLX5_SET(mkc, mkc, length64, 1);
MLX5_SET(mkc, mkc, qpn, 0xffffff);
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
index c3c2c5720c6f..efd69b1bfb59 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
@@ -462,7 +462,7 @@ static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
MLX5_SET(mkc, mkc, lw, 1);
MLX5_SET(mkc, mkc, lr, 1);
MLX5_SET(mkc, mkc, access_mode_1_0, mlx5e_mpwrq_access_mode(umr_mode));
- mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
+ mlx5_core_mkey_set_ordering(mdev, mkc, MLX5_MKEY_ORDER_RELAXED);
MLX5_SET(mkc, mkc, qpn, 0xffffff);
MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
MLX5_SET64(mkc, mkc, len, npages << page_shift);
@@ -801,7 +801,7 @@ static int mlx5e_create_rq_hd_mkey(struct mlx5_core_dev *mdev,
MLX5_SET(mkc, mkc, lw, 1);
MLX5_SET(mkc, mkc, lr, 1);
MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
- mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
+ mlx5_core_mkey_set_ordering(mdev, mkc, MLX5_MKEY_ORDER_RELAXED);
MLX5_SET(mkc, mkc, qpn, 0xffffff);
MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
MLX5_SET64(mkc, mkc, len, shampo->hd_buf_size);
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mr.c b/drivers/net/ethernet/mellanox/mlx5/core/mr.c
index 678f0be81375..eced7d24948c 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/mr.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/mr.c
@@ -35,6 +35,38 @@
#include <linux/mlx5/qp.h>
#include "mlx5_core.h"
+/**
+ * mlx5_core_mkey_set_ordering - Set ordering flags in mkey context
+ * @dev: MLX5 core device
+ * @mkc: Memory key context buffer
+ * @order: Requested ordering level
+ *
+ * Sets the ordering fields in @mkc for @order based on device caps. Call when
+ * creating or modifying a memory key. MLX5_MKEY_ORDER_STRICT leaves @mkc as is.
+ */
+void mlx5_core_mkey_set_ordering(struct mlx5_core_dev *dev, void *mkc,
+ enum mlx5_mkey_order order)
+{
+ bool ro_write, ro_read;
+
+ if (order == MLX5_MKEY_ORDER_STRICT)
+ return;
+
+ ro_write = MLX5_CAP_GEN(dev, mkc_order_write_after_write_ro);
+ ro_read = MLX5_CAP_GEN(dev, pci_relaxed_ordered_read) ||
+ (MLX5_CAP_GEN(dev, relaxed_ordering_read_pci_enabled) &&
+ pcie_relaxed_ordering_enabled(dev->pdev));
+
+ MLX5_SET(mkc, mkc, pci_relaxed_ordered_read, ro_read);
+ MLX5_SET(mkc, mkc, order_write_after_write, ro_write);
+
+ if (order == MLX5_MKEY_ORDER_UNORDERED &&
+ MLX5_CAP_GEN(dev, mkc_order_read_after_write))
+ MLX5_SET(mkc, mkc, order_read_after_write,
+ MLX5_MKC_ORDER_READ_AFTER_WRITE_RO);
+}
+EXPORT_SYMBOL(mlx5_core_mkey_set_ordering);
+
int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
int inlen)
{
diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
index abb99371ff13..901744e3d63a 100644
--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -697,6 +697,12 @@ enum mlx5_sw_icm_type {
MLX5_SW_ICM_TYPE_SW_ENCAP,
};
+enum mlx5_mkey_order {
+ MLX5_MKEY_ORDER_STRICT,
+ MLX5_MKEY_ORDER_RELAXED,
+ MLX5_MKEY_ORDER_UNORDERED,
+};
+
#define MLX5_MAX_RESERVED_GIDS 8
struct mlx5_rsvd_gids {
@@ -1037,6 +1043,8 @@ void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
struct mlx5_frag_buf *buf, int node);
void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
+void mlx5_core_mkey_set_ordering(struct mlx5_core_dev *dev, void *mkc,
+ enum mlx5_mkey_order order);
int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
int inlen);
int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
--
2.52.0
next prev parent reply other threads:[~2026-11-02 22:34 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20261102223325.2115128-1-michaelgur@nvidia.com>
2026-11-02 22:32 ` [PATCH rdma-next v2 01/15] RDMA/mlx5: Allow optional access flags in DM registration Michael Gur
2026-11-02 22:32 ` [PATCH rdma-next v2 02/15] RDMA/mlx5: Allow optional access flags in DEVX UMEM registration Michael Gur
2026-11-02 22:32 ` [PATCH rdma-next v2 03/15] RDMA/core: Allow optional access flags in dmabuf reg ioctl Michael Gur
2026-11-02 22:32 ` [PATCH rdma-next v2 04/15] RDMA/core: Allow optional access flags in reg mr ioctl Michael Gur
2026-11-02 22:32 ` [PATCH rdma-next v2 05/15] mlx5: Rename IFC bits of relaxed ordering fields Michael Gur
2026-11-02 22:32 ` [PATCH rdma-next v2 06/15] net/mlx5: Add IFC bits for new ordering caps Michael Gur
2026-11-02 22:33 ` Michael Gur [this message]
2026-11-02 22:33 ` [PATCH rdma-next v2 08/15] net/mlx5: Enable relaxed ordering on resource dump mkey Michael Gur
2026-11-02 22:33 ` [PATCH rdma-next v2 09/15] net/mlx5: Enable relaxed ordering on FW tracer mkey Michael Gur
2026-11-02 22:33 ` [PATCH rdma-next v2 10/15] vfio/mlx5: Enable relaxed ordering on the live migration data mkey Michael Gur
2026-11-02 22:33 ` [PATCH rdma-next v2 11/15] RDMA/mlx5: Enable relaxed ordering on ODP null mkey Michael Gur
2026-11-02 22:33 ` [PATCH rdma-next v2 12/15] RDMA/mlx5: Converge UMR access-flag cap checks Michael Gur
2026-11-02 22:33 ` [PATCH rdma-next v2 13/15] RDMA/uverbs: Add new Unordered MR access flag Michael Gur
2026-11-02 22:33 ` [PATCH rdma-next v2 14/15] RDMA/mlx5: Support new Unordered " Michael Gur
2026-11-02 22:33 ` [PATCH rdma-next v2 15/15] RDMA/mlx5: Enforce relaxed ordering when HW requires it Michael Gur
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