On Tue, Nov 03, 2026 at 04:11:24PM +0100, Aleksa Paunovic via B4 Relay wrote:
> The MIPS P8700 is a multi-core RISC-V microprocessor system, supporting
> both single-cluster and multi-cluster configurations. [1]
> This series adds full description of the platform,
> including the Boston FPGA board configured with a P8700 bitfile.
> 
> The P8700 cores support the RV64GCZba_Zbb (G = IMAFD) Standard ISA,
> with a caveat: the A extension is only partially supported, and all ZAAMO
> extension instructions are emulated on the SBI level. The device tree
> intentionally does not reflect this fact. Vladimir Kondratiev's series
> improves performance by directly substituting AMO instructions with LR/SC. [4]
> The two patchsets do not depend on one another.
> 
> The board itself is the same board as 'img,boston', configured with a different
> bitfile [3]. The Boston board has been supported since commit 6e62a888029b
> ("MIPS: generic: Support MIPS Boston development boards") (thanks to Maciej for finding the ref).
> 
> GlobalFoundries has acquired MIPS [2] and the vendor prefix
> for all newly added MIPS RISC-V hardware reflects that fact.
> 
> I tested this series both on QEMU and a Boston board
> configured with a single P8700 CPU,
> after applying the necessary U-Boot and OpenSBI changes
> to match the 'compatible' strings and the changed MTIMER register order.
> We are planning to upstream these as well.
> 
> Links:
> [1] https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf
> [2] https://gf.com/news-and-events/news/globalfoundries-completes-acquisition-of-mips/
> [3] https://training.mips.com/cps_mips/Examples/MD00901_Boot-MIPS_Example_Boot_Code_for_MIPS_Cores.pdf
> [4] https://lore.kernel.org/all/20261026-lrsc-only-v3-0-ec29c8190fb1@mobileye.com/
> 
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> ---
> Changes in v2:
> - Patch 1: Replace "MIPS Technology" with "MIPS Technologies".
> - Patch 3: Name the FPGA used and add the versioned bitfile compatible.
> - Patch 5: Drop hart indexes from MSWI.
> - Patch 6: Swap mtimecmp and mtime, require reg-names both for mtime and mtimecmp on P8700.
> - Original patch 7: Dropped.
> - Patch 7 (previously 8): Remove additional harts that are not
>   present in the bitfile I have. Reflect changes made in patches 3, 5 and 6.
>   Remove riscv,cbom-block-size. Drop undocumented compatibles. Other minor changes.
> - Link to v1: https://lore.kernel.org/r/20260914-p8700-dts-v1-0-3267f14ebce1@htecgroup.com
> 
> ---
> Aleksa Paunovic (8):
>       dt-bindings: vendor-prefixes: Add GlobalFoundries, Inc.
>       dt-bindings: riscv: cpus: add gf,mips-p8700
>       dt-bindings: riscv: Add MIPS Boston board compatible
>       dt-bindings: interrupt-controller: Add MIPS P8700 APLIC
>       dt-bindings: interrupt-controller: Add MIPS P8700 ACLINT MSWI
>       dt-bindings: timer: Add MIPS P8700 ACLINT MTIMER
>       riscv: dts: gf: Initial support for the P8700 Boston board
>       riscv: defconfig: Enable GF SoCs
> 
>  .../bindings/interrupt-controller/riscv,aplic.yaml |   1 +
>  .../thead,c900-aclint-mswi.yaml                    |  11 ++
>  Documentation/devicetree/bindings/riscv/cpus.yaml  |   1 +
>  Documentation/devicetree/bindings/riscv/gf.yaml    |  33 +++++
>  .../bindings/timer/thead,c900-aclint-mtimer.yaml   |  35 ++++++
>  .../devicetree/bindings/vendor-prefixes.yaml       |   4 +-
>  arch/riscv/Kconfig.socs                            |   6 +
>  arch/riscv/boot/dts/Makefile                       |   1 +
>  arch/riscv/boot/dts/gf/Makefile                    |   2 +
>  arch/riscv/boot/dts/gf/p8700-boston.dts            | 135 +++++++++++++++++++++
>  arch/riscv/boot/dts/gf/p8700.dtsi                  |  82 +++++++++++++
>  arch/riscv/configs/defconfig                       |   1 +
>  12 files changed, 311 insertions(+), 1 deletion(-)

You're missing a MAINTAINERS entry for the platform, since someone is
going to have to pick up the patches for the arch/riscv/boot/dts/gf and
that someone is neither Palmer nor Paul.
See Documentation/process/maintainer-soc.rst for more info.

I'd apply patches as a very last resort, but even then you'd need an entry
to make sure that you're CCed on patches for the platform because I
don't care about the platform and would just apply things that look
correct if there was no reviews provided.

Cheers,
Conor.