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Tue, 03 Nov 2026 12:37:52 -0800 (PST) Received: from localhost ([2600:1702:7a90:6f9f:8bc4:8aec:108d:7a04]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-67bee285be7sm143757d50.16.2026.11.03.12.37.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 12:37:51 -0800 (PST) From: Matt Turner Date: Tue, 03 Nov 2026 15:37:42 -0500 Subject: [PATCH v5 09/11] alpha/perf: report the data source of ProfileMe DTB misses X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261103-alpha-profileme-v5-9-bbe3937fbf3a@gmail.com> References: <20261103-alpha-profileme-v5-0-bbe3937fbf3a@gmail.com> In-Reply-To: <20261103-alpha-profileme-v5-0-bbe3937fbf3a@gmail.com> To: Richard Henderson , Magnus Lindholm , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark Cc: linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Matt Turner X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4260; i=mattst88@gmail.com; h=from:subject:message-id; bh=ThdyPtCDGcliaCjOAS0KHbzlPZhBU/4z3/FVVxSxIz4=; b=owGbwMvMwCW25rVmCc8sv+mMp9WSGLJeufFZ3HF8uKFXOPbU6aAJYtv+xfUr318VUznpfEuiy o143vKjHR9ZGMS4GGaKKbLErVdkmdW2Y6nPaelfMHNYmUCGSIs0MAABCwNfbmJeqZGOkZ6ptqGe IZChYxQPkdNj0MgsLi5NLdJNKyhyyMsvSSzJzM8r1ssvSM0rSC/QS8tMK8nIyC8qTgUaoZeXWmL q6uhmZGhgYuloYeZk4Whq4uzsZOjk5ujo7OpkZGluYuBs6WjiamnOwMUpAHPNA0+G/4FfFGplYt /GbxfdfbFXcfmstgtGC1quzpSdzLW3TdBY0Ijhf3TubYM3RjJphlOLlv+7X339b7DMbK6F35+He udsWjb9BCMA X-Developer-Key: i=mattst88@gmail.com; a=openpgp; fpr=3BB639E56F861FA2E86505690FDD682D974CA72A A ProfileMe sample whose instruction trapped on a DTB miss identifies a memory access that missed the DTB, but only in the PERF_SAMPLE_RAW data. Set PERF_SAMPLE_DATA_SRC for those samples, so that the memory sort keys see them: mem_dtlb is an L1 miss, and mem_op comes from the opcode, as I_STAT does not say whether the access was a load or a store. Samples that fall back to the interrupted PC get none. I_STAT[TRP] is ignored for an instruction killed before it was mapped. On an EV7, TRP and MIS were seen set for killed instructions that are not even branches. Suggested-by: Ian Rogers Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Matt Turner --- arch/alpha/include/asm/wrperfmon.h | 11 ++++++++ arch/alpha/kernel/perf_event.c | 51 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/arch/alpha/include/asm/wrperfmon.h b/arch/alpha/include/asm/wrperfmon.h index 7fbbfd74926a..489b3e073a32 100644 --- a/arch/alpha/include/asm/wrperfmon.h +++ b/arch/alpha/include/asm/wrperfmon.h @@ -100,6 +100,17 @@ /* ProfileMe status, from the EV67/EV68 Hardware Reference Manuals. */ #define EV67_I_STAT_OVR_SHIFT 30 #define EV67_I_STAT_OVR_MASK 0x7UL +#define EV67_I_STAT_TRAP_TYPE_SHIFT 34 +#define EV67_I_STAT_TRAP_TYPE_MASK 0xfUL +#define EV67_I_STAT_TRP (1UL<<39) +#define EV67_I_STAT_MIS (1UL<<40) + +/* I_STAT[TRAP_TYPE] values */ +#define EV67_TRAP_DTB_DOUBLE_3 2 +#define EV67_TRAP_DTB_DOUBLE_4 3 +#define EV67_TRAP_DTB_SINGLE 6 + +#define EV67_PCTR_PM_KILLED_BM (1UL<<26) /* PMPC bits 63:2 hold the profiled PC. Bit 0 set means a PALmode address. */ #define EV67_PMPC_PAL (1UL<<0) diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c index c2c367b51617..7f53aea261b0 100644 --- a/arch/alpha/kernel/perf_event.c +++ b/arch/alpha/kernel/perf_event.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -1015,6 +1016,39 @@ static void alpha_profileme_set_regs_user(struct perf_event *event, sizeof(u64); } +/* TRP, and MIS with it, are stale for an insn killed before it was mapped. */ +static bool alpha_profileme_trp(unsigned long i_stat, unsigned long pctr_ctl) +{ + return !(pctr_ctl & EV67_PCTR_PM_KILLED_BM) && (i_stat & EV67_I_STAT_TRP); +} + +static u64 alpha_profileme_mem_op(unsigned long pc) +{ + u32 insn; + + if (pc < TASK_SIZE) { + if (copy_from_user_nofault(&insn, (const void __user *)pc, + sizeof(insn))) + return PERF_MEM_OP_NA; + } else if (copy_from_kernel_nofault(&insn, (const void *)pc, + sizeof(insn))) { + return PERF_MEM_OP_NA; + } + + switch (insn >> 26) { + case 0x0a: case 0x0b: case 0x0c: /* ldbu, ldq_u, ldwu */ + case 0x20: case 0x21: case 0x22: case 0x23: /* ldf, ldg, lds, ldt */ + case 0x28: case 0x29: case 0x2a: case 0x2b: /* ldl, ldq, ldl_l, ldq_l */ + return PERF_MEM_OP_LOAD; + case 0x0d: case 0x0e: case 0x0f: /* stw, stb, stq_u */ + case 0x24: case 0x25: case 0x26: case 0x27: /* stf, stg, sts, stt */ + case 0x2c: case 0x2d: case 0x2e: case 0x2f: /* stl, stq, stl_c, stq_c */ + return PERF_MEM_OP_STORE; + default: + return PERF_MEM_OP_NA; + } +} + /* * Handle the close of a ProfileMe window on PCTR0. * @@ -1130,6 +1164,23 @@ static void alpha_perf_event_profileme(struct perf_event *event, data.sample_flags |= PERF_SAMPLE_WEIGHT_TYPE; } + if (exact && (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) && + alpha_profileme_trp(i_stat, pctr_ctl) && + !(i_stat & EV67_I_STAT_MIS)) { + switch ((i_stat >> EV67_I_STAT_TRAP_TYPE_SHIFT) & + EV67_I_STAT_TRAP_TYPE_MASK) { + case EV67_TRAP_DTB_SINGLE: + case EV67_TRAP_DTB_DOUBLE_3: + case EV67_TRAP_DTB_DOUBLE_4: + data.data_src.val = PERF_MEM_NA; + data.data_src.mem_op = alpha_profileme_mem_op(pc); + data.data_src.mem_dtlb = PERF_MEM_TLB_L1 | + PERF_MEM_TLB_MISS; + data.sample_flags |= PERF_SAMPLE_DATA_SRC; + break; + } + } + if (!alpha_perf_event_set_period(event, hwc, 0)) return; -- 2.55.0