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Miller" , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Matthias Brugger , AngeloGioacchino Del Regno , Biao Huang , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Eric Dumazet , Eric Dumazet Cc: kernel@collabora.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793700755; l=3068; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=k7BZVTEhl5+fKOqiVRSm79Wa3lEDitEyKq/JHBxPr40=; b=NXZ3cYbw9gUeF00vWjN84Y97ZzmgU/JNsRs8keF+MYefD6nDwe+WRQAiz5oZmafZzDQYXUQ6W dBqVy7L3cZyBDZKeN9871nAsFrUrSKH8I3q0xdqFH9b+ap5/6qaUfot X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Like MT8195 SoC, MT8189 SoC uses the Ethernet control registers from the peripheral configuration (pericfg) but at a different offset. It also has different RX and TX internal delay stage dividers (290ps for MT8195, 180ps for MT8189), and by consequence a reduced value range for these delays. It finally needs additional feature such as the TX clock output enable one. Thus, add compatible, clock definitions and specific platform data to support the MT8189 SoC. Signed-off-by: Louis-Alexis Eyraud --- .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c index 8ee850791270..07d0c186ab65 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -42,8 +42,15 @@ #define MT2712_RGMII_DELAY_MAX 5440 /* 32 x 170ps */ /* Peri Configuration register for mt8189 */ +#define MT8189_PERI_ETH_CTRL_OFFSET 0x270 + #define MT8189_CTRL0_TXC_OUT_OP_EN BIT(20) +#define MT8189_MII_DLY_STAGE_DIV 180 /* 180ps per stage */ +#define MT8189_MII_DELAY_MAX 5760 /* 32 x 180ps */ +#define MT8189_RGMII_DLY_STAGE_DIV 180 /* 180ps per stage */ +#define MT8189_RGMII_DELAY_MAX 5760 /* 32 x 180ps */ + /* Peri Configuration register for mt8195 */ #define MT8195_PERI_ETH_CTRL_OFFSET 0xFD0 @@ -124,6 +131,10 @@ static const char * const mt2712_dwmac_clk_l[] = { "axi", "apb", "mac_main", "ptp_ref" }; +static const char * const mt8189_dwmac_clk_l[] = { + "axi", "apb", "mac_main", "ptp_ref" +}; + static const char * const mt8195_dwmac_clk_l[] = { "axi", "apb", "mac_cg", "mac_main", "ptp_ref" }; @@ -440,6 +451,20 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat) return 0; } +static const struct mediatek_dwmac_variant mt8189_gmac_variant = { + .dwmac_set_phy_interface = mt8195_set_interface, + .dwmac_set_delay = mt8195_set_delay, + .clk_list = mt8189_dwmac_clk_l, + .num_clks = ARRAY_SIZE(mt8189_dwmac_clk_l), + .dma_bit_mask = 35, + .mii_delay_max = MT8189_MII_DELAY_MAX, + .rgmii_delay_max = MT8189_RGMII_DELAY_MAX, + .mii_delay_stage_div = MT8189_MII_DLY_STAGE_DIV, + .rgmii_delay_stage_div = MT8189_RGMII_DLY_STAGE_DIV, + .peri_eth_ctrl_offset = MT8189_PERI_ETH_CTRL_OFFSET, + .mac_txclk_out_en = true, +}; + static const struct mediatek_dwmac_variant mt8195_gmac_variant = { .dwmac_set_phy_interface = mt8195_set_interface, .dwmac_set_delay = mt8195_set_delay, @@ -727,6 +752,8 @@ static void mediatek_dwmac_remove(struct platform_device *pdev) static const struct of_device_id mediatek_dwmac_match[] = { { .compatible = "mediatek,mt2712-gmac", .data = &mt2712_gmac_variant }, + { .compatible = "mediatek,mt8189-gmac", + .data = &mt8189_gmac_variant }, { .compatible = "mediatek,mt8195-gmac", .data = &mt8195_gmac_variant }, { } -- 2.56.0