From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=148.251.105.195 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793700767; b=lLObJWYjtStddJ+uetPz9CXqC9asw78Act8ze/6u0txlmrbYBbRHekYzg0mFqOkeNKfr /A+mg1feolLuliaOdM//RCO9Hl9p91QW7y0Je2xsFr5VWYhBSHDjdaBw8+VxydKM8z0R5 j4uivgdHBs8qKtOhcI3fKy9S8gDK4Q3JgqFhnUVJRgGe/kgRGuZ80xBLKY5mTJ150JvN3 fs1DtFhBEAJj5OYIGR9JEG0Du+y0hjF8D+SPj/D33/yijdnvzFgqvPPYsnvsdnV+/UeWG 2JKC9EdAzYS5VTBZoFkWbZI4fcraVg9B1GFYwSs/VovgB0Nn460Usj8+1ugkXuKaQ9Q== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793700767; h=DMARC-Filter:DKIM-Signature:Received:From:Date:Subject:MIME-Version: Content-Type:Content-Transfer-Encoding:Message-Id:References: In-Reply-To:To:Cc:X-Mailer:X-Developer-Signature:X-Developer-Key; bh=YzQBxDywg53L/d7II1zv+CoUHO7/4sl0WQuSbexemXU=; b=WZ2YXSU5480NzYd1NyMhs1qfMN3z36A5uzenlHudIUTX1syoZ/06z6GZ++KTgSFB6+nQ ELM1oYqMrjgzMLKXNAeR39BYf15f9HB0Q84jqm/QV85bpQiqdnpvAcukLjQCCTw/b5wAy yB0zOHc3OBB1SYw+iG1X1S2s2YE1PVzkIQV8ENsL2kdDtfFQQWeMx1PLPsbG+Xn8ne5qc 7sK9n+Y70gGxGYcygy/2+bUX4agJOxxhqdo0MGIIGvjSNUZ73rJevA49AbkaSwKwElXdR xgnP58FY5CpbDd81cH7opJC80JODVpeuFFydl6quvJ5tYT7vRzUls+YAGJtV/vVjA+w== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass header.d=collabora.com header.i=@collabora.com header.a=rsa-sha256 header.s=mail header.b=bT4qjTDD; arc=none smtp.remote-ip=148.251.105.195 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68FF0606D836; Tue, 3 Nov 2026 10:12:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org 68FF0606D836 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=collabora.com header.i=@collabora.com header.a=rsa-sha256 header.s=mail header.b=bT4qjTDD DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1793700764; bh=fgRG/Qp5WV1QVNiuGm1kV55/qVJ1752aXcE75rXacDY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=bT4qjTDD8nhVuE2QOXMBQeQQzT9j7dnABNRCT9UJTxfgA11T5bhdPr+OrFwgS3k3H 1TFoQ6IlZ66BJ1yGFj6SsLoMONaohJZEMci8HJp5uFvcHLBqYy3ncsUYOhiolCp1T0 QF+6MjpZdtHCDcNMeXVQ9nvxcQHqpsJ97GSOI+u2kx4LibG4hmI/SPE7EYX1PCpqEJ qqCqyJTt1wcTJ1+UiG4bVrcdCwgAjjohREhcQyQudxILPc8tY7MGQRP/Vs6EFSbWi7 miNowF+/QwjxQApfKuI6c8f5WPsKBZlQoPOVhyoxYZIdgLh6U8i/aFZbSDDxae1fNJ 7u/tHcq6nNxBQ== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id EAEC317E0D48; Tue, 03 Nov 2026 11:12:43 +0100 (CET) From: Louis-Alexis Eyraud Date: Tue, 03 Nov 2026 11:12:13 +0100 Subject: [PATCH net-next v4 08/10] net: stmmac: mediatek: add PERI_ETH_CTRLx register offset in platform data X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261103-dwmac-mediatek-mt8189-v4-8-c86c14fc50f4@collabora.com> References: <20261103-dwmac-mediatek-mt8189-v4-0-c86c14fc50f4@collabora.com> In-Reply-To: <20261103-dwmac-mediatek-mt8189-v4-0-c86c14fc50f4@collabora.com> To: Andrew Lunn , "David S. Miller" , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Matthias Brugger , AngeloGioacchino Del Regno , Biao Huang , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Eric Dumazet , Eric Dumazet Cc: kernel@collabora.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793700755; l=4252; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=fgRG/Qp5WV1QVNiuGm1kV55/qVJ1752aXcE75rXacDY=; b=3v6Sd2ufLqjqoYS8sbLNQO/XBHltzdUWz8j+vLUnIhNiWcExXGEmDeterfwVsw0ebv1vF9Ba1 nzA+ia0C0NZDE/XXT777Lp+tCfntNgoBtcmkpyrHV7eDl9vtD64ymXx X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= In preparation of newer SoC support, that use like MT8195 the Ethernet control registers from the peripheral configuration syscon but at a different base offset, add a new base offset in the variant platform data to access the PERI_ETH_CTRLx registers and use it in implemented methods. Reviewed-by: Maxime Chevallier Signed-off-by: Louis-Alexis Eyraud --- .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 26 ++++++++++++++++------ 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c index 61bc1ff08cc4..0426a0876956 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -42,7 +42,9 @@ #define MT2712_RGMII_DELAY_MAX 5440 /* 32 x 170ps */ /* Peri Configuration register for mt8195 */ -#define MT8195_PERI_ETH_CTRL0 0xFD0 +#define MT8195_PERI_ETH_CTRL_OFFSET 0xFD0 + +#define MT8195_PERI_ETH_CTRL0 0x0 #define MT8195_RMII_CLK_SRC_INTERNAL BIT(28) #define MT8195_RMII_CLK_SRC_RXC BIT(27) #define MT8195_ETH_INTF_SEL GENMASK(26, 24) @@ -52,7 +54,7 @@ #define MT8195_DLY_GTXC_ENABLE BIT(5) #define MT8195_DLY_GTXC_STAGES GENMASK(4, 0) -#define MT8195_PERI_ETH_CTRL1 0xFD4 +#define MT8195_PERI_ETH_CTRL1 0x4 #define MT8195_DLY_RXC_INV BIT(25) #define MT8195_DLY_RXC_ENABLE BIT(18) #define MT8195_DLY_RXC_STAGES GENMASK(17, 13) @@ -60,7 +62,7 @@ #define MT8195_DLY_TXC_ENABLE BIT(5) #define MT8195_DLY_TXC_STAGES GENMASK(4, 0) -#define MT8195_PERI_ETH_CTRL2 0xFD8 +#define MT8195_PERI_ETH_CTRL2 0x8 #define MT8195_DLY_RMII_RXC_INV BIT(25) #define MT8195_DLY_RMII_RXC_ENABLE BIT(18) #define MT8195_DLY_RMII_RXC_STAGES GENMASK(17, 13) @@ -109,6 +111,7 @@ struct mediatek_dwmac_variant { u32 rgmii_delay_max; u16 mii_delay_stage_div; u16 rgmii_delay_stage_div; + u32 peri_eth_ctrl_offset; u8 dma_bit_mask; }; @@ -292,6 +295,7 @@ static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat, u8 phy_intf_sel) { u32 intf_val = FIELD_PREP(MT8195_ETH_INTF_SEL, phy_intf_sel); + u32 reg_offset = plat->variant->peri_eth_ctrl_offset; if (phy_intf_sel == PHY_INTF_SEL_RMII) { if (plat->rmii_clk_from_mac) @@ -303,7 +307,9 @@ static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat, /* MT8195 only support external PHY */ intf_val |= MT8195_EXT_PHY_MODE; - regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL0, intf_val); + regmap_write(plat->peri_regmap, + reg_offset + MT8195_PERI_ETH_CTRL0, + intf_val); return 0; } @@ -311,6 +317,7 @@ static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat, static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat) { struct mac_delay_struct *mac_delay = &plat->mac_delay; + u32 reg_offset = plat->variant->peri_eth_ctrl_offset; u32 rx_delay_stage_val, tx_delay_stage_val; u32 gtxc_delay_val = 0; u32 rmii_delay_val = 0; @@ -410,14 +417,18 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat) } regmap_update_bits(plat->peri_regmap, - MT8195_PERI_ETH_CTRL0, + reg_offset + MT8195_PERI_ETH_CTRL0, MT8195_RGMII_TXC_PHASE_CTRL | MT8195_DLY_GTXC_INV | MT8195_DLY_GTXC_ENABLE | MT8195_DLY_GTXC_STAGES, gtxc_delay_val); - regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL1, delay_val); - regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL2, rmii_delay_val); + regmap_write(plat->peri_regmap, + reg_offset + MT8195_PERI_ETH_CTRL1, + delay_val); + regmap_write(plat->peri_regmap, + reg_offset + MT8195_PERI_ETH_CTRL2, + rmii_delay_val); return 0; } @@ -432,6 +443,7 @@ static const struct mediatek_dwmac_variant mt8195_gmac_variant = { .mii_delay_stage_div = MT8195_MII_DLY_STAGE_DIV, .rgmii_delay_stage_div = MT8195_RGMII_DLY_STAGE_DIV, .dma_bit_mask = 35, + .peri_eth_ctrl_offset = MT8195_PERI_ETH_CTRL_OFFSET, }; static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat) -- 2.56.0