From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793706138; b=2xQIMWA3O2GXt1jjL5NgP2JQ0JJmw1NRK0t9GczKs9wvvtTl1mGg2tHLKPtuMMeH6xNC XIevTKk1+Ie08TMgxALnCo7h651qy7sMCf5ky78wrZnAUlBgg4dZQH0fpBghI/ZsfmaTh lrSe0RoRp0aipEkUyOF7LOcSMGeqb20cMTl3SQArK+FSzfrnconAOEosg77Wvwgn/gng5 GOzeMyiZqiwTawySbego2zHhmAHEjoo+lbt8x188VtZ2b+MFGMhmq0rwyKBui5pIyANgl Phm2d0RYvOT14RhIGNMLmlmgN4Y88TBm/6WHD52rafJ0z2hkCrj24dX4bERmM4Fp1KQ== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793706138; h=Received:DKIM-Signature:Date:From:To:Cc:Subject:Message-ID: References:MIME-Version:Content-Type:Content-Disposition:In-Reply-To; bh=JtnP2Kmt3o513W8ZN25ivNSHMfIQTn2OfI3LInIkTz8=; b=LHnwO6J8oJK1mt25L+i0LU+1s63sjh3IAJ7oG6puyUYw5StWSvh9uJ9L9brnXwxDTgAi i8SodgfH+urM56Eh5HFgorJBjTuchaxlndvGwQq0hP5i0g3kyIvzVja60DpW1PRPQ4iKd IZCNGabwJdBO3nlqZ6BVgDMMt+FX6XVancufvJMl8V9+Rgt7AstjsRMdBIof6up0k8lcA Bjuxt3uNsnNkuy9FwQt0xCGJqJJNyLb04VrzCL/28qTPq24S6h+b82oGJY1sQr/FSQ2G0 TwtFpHWbr+n5n6lc3RLrVMXGRaP5iOPzfbhlt7pzWGToR39qDFGFbTuoX9mX3rDaZcA== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=IXpnNgIN; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1E5A60A2612; Tue, 3 Nov 2026 11:42:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=IXpnNgIN Received: by smtp.kernel.org (Postfix) with ESMTPSA id AC0461F00A1F; Tue, 3 Nov 2026 11:42:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793706137; bh=JtnP2Kmt3o513W8ZN25ivNSHMfIQTn2OfI3LInIkTz8=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=IXpnNgINgSEAHEMFXORCm01bjHLe8Jqzudl5gkpcqfqYTic8HdXBqs0qpuCJDm7L5 ZiSlZQ5u+EjuWfkIiICpeC5Bk9y6MvV09noWc+p/eUl36tmfHISFjgf8acE8hAXnqm hAN4CAALutN7phmY1DIlm6jT71dFHeB1MCIetJC3/nBznVar4F0hfhTjTPNuYmNMWc Y6B2f+R3wFHoQEj6rQYPB3FW3mqr0eyC7eJSaa3jftESdkUE+gre1VLbagAwtiF1rz XdfP2+a6ruN5wStDTJibT04KZ2dXVwwZFJUPit86hTSpwq4ujenKTKomXcUSH+iuNH E01gXC4DDPD4w== Date: Tue, 3 Nov 2026 12:42:14 +0100 From: Krzysztof Kozlowski To: Junyi Zhao Cc: Alexandre Belloni , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Miquel Raynal , Kees Cook , "Gustavo A. R. Silva" , linux-i3c@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, imx@lists.linux.dev, linux-hardening@vger.kernel.org, xianwei.zhao@amlogic.com, Kelvin.Zhang@amlogic.com Subject: Re: [PATCH v2 2/2] dt-bindings: i3c: silvaco,i3c-master: Add Amlogic A9 support Message-ID: <20261103-emotional-objective-jaybird-0627b5@quoll> References: <20261102-a9_i3c-v2-0-0c474bfccffa@amlogic.com> <20261102-a9_i3c-v2-2-0c474bfccffa@amlogic.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20261102-a9_i3c-v2-2-0c474bfccffa@amlogic.com> On Mon, Nov 02, 2026 at 07:05:40PM +0800, Junyi Zhao wrote: > Amlogic A9 SoCs integrate the Silvaco I3C IP with two controller > instances: > > - amlogic,a9-i3c for the EE domain, which takes two clocks, > "pclk" and "fast_clk" like the NXP variants; > > - amlogic,a9-ao-i3c for the Always-On (AO) domain, which exposes > only "pclk": its bus clock is generated by an internal divider > located in the controller's own register space. > > Allow both compatibles with the "silvaco,i3c-master-v1" fallback and > enforce the per-variant clock counts. This we see in the diff, but we do not see WHY. Best regards, Krzysztof