From: Aleksa Paunovic via B4 Relay <devnull+aleksa.paunovic.htecgroup.com@kernel.org>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Djordje Todorovic <djordje.todorovic@htecgroup.com>,
Anup Patel <anup@brainfault.org>,
Thomas Gleixner <tglx@kernel.org>, Radu Rendec <radu@rendec.net>,
Inochi Amaoto <inochiama@outlook.com>,
Daniel Lezcano <daniel.lezcano@kernel.org>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Conor Dooley <conor@kernel.org>,
linux-riscv@lists.infradead.org,
Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@sifive.com>,
Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
Subject: [PATCH v2 5/8] dt-bindings: interrupt-controller: Add MIPS P8700 ACLINT MSWI
Date: Tue, 03 Nov 2026 16:11:29 +0100 [thread overview]
Message-ID: <20261103-p8700-dts-v2-5-3ac5d49f2c37@htecgroup.com> (raw)
In-Reply-To: <20261103-p8700-dts-v2-0-3ac5d49f2c37@htecgroup.com>
From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
Document the aclint mswi compatible for the MIPS P8700.
Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
.../bindings/interrupt-controller/thead,c900-aclint-mswi.yaml | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
index 62fd220e126e650e3800d8eee2a749fdbbde6108..ca91b650caab8927b3a4ed91f1f7f142e3790a97 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
@@ -21,6 +21,7 @@ properties:
- enum:
- anlogic,dr1v90-aclint-mswi
- const: nuclei,ux900-aclint-mswi
+ - const: gf,mips-p8700-aclint-mswi
reg:
maxItems: 1
@@ -46,4 +47,14 @@ examples:
<&cpu4intc 3>;
reg = <0x94000000 0x00010000>;
};
+
+ - |
+ mswi@16150000 {
+ compatible = "gf,mips-p8700-aclint-mswi";
+ reg = <0x16150000 0x4000>;
+ interrupts-extended = <&cpu1intc 3>,
+ <&cpu2intc 3>,
+ <&cpu3intc 3>,
+ <&cpu4intc 3>;
+ };
...
--
2.43.0
next prev parent reply other threads:[~2026-11-03 15:11 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-03 15:11 [PATCH v2 0/8] Add support for MIPS P8700 Aleksa Paunovic via B4 Relay
2026-11-03 15:11 ` [PATCH v2 1/8] dt-bindings: vendor-prefixes: Add GlobalFoundries, Inc Aleksa Paunovic via B4 Relay
2026-11-03 15:11 ` [PATCH v2 2/8] dt-bindings: riscv: cpus: add gf,mips-p8700 Aleksa Paunovic via B4 Relay
2026-11-03 21:46 ` Conor Dooley
2026-11-03 15:11 ` [PATCH v2 3/8] dt-bindings: riscv: Add MIPS Boston board compatible Aleksa Paunovic via B4 Relay
2026-11-03 21:43 ` Conor Dooley
2026-11-03 15:11 ` [PATCH v2 4/8] dt-bindings: interrupt-controller: Add MIPS P8700 APLIC Aleksa Paunovic via B4 Relay
2026-11-03 21:46 ` Conor Dooley
2026-11-03 15:11 ` Aleksa Paunovic via B4 Relay [this message]
2026-11-03 21:51 ` [PATCH v2 5/8] dt-bindings: interrupt-controller: Add MIPS P8700 ACLINT MSWI Conor Dooley
2026-11-03 15:11 ` [PATCH v2 6/8] dt-bindings: timer: Add MIPS P8700 ACLINT MTIMER Aleksa Paunovic via B4 Relay
2026-11-03 21:49 ` Conor Dooley
2026-11-03 15:11 ` [PATCH v2 7/8] riscv: dts: gf: Initial support for the P8700 Boston board Aleksa Paunovic via B4 Relay
2026-11-03 21:51 ` Conor Dooley
2026-11-03 15:11 ` [PATCH v2 8/8] riscv: defconfig: Enable GF SoCs Aleksa Paunovic via B4 Relay
2026-11-03 21:47 ` Conor Dooley
2026-11-03 21:59 ` [PATCH v2 0/8] Add support for MIPS P8700 Conor Dooley
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