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Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe , Yishai Hadas CC: Edward Srouji , , , , Mark Bloch , Michael Gur , Patrisious Haddad Subject: [PATCH mlx5-next 1/5] net/mlx5: Add NIC_RX_CLASS IFC bits Date: Tue, 3 Nov 2026 20:12:49 +0200 Message-ID: <20261103-rdma-rx-classifier-v1-1-1ad6c8cfe936@nvidia.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20261103-rdma-rx-classifier-v1-0-1ad6c8cfe936@nvidia.com> References: <20261103-rdma-rx-classifier-v1-0-1ad6c8cfe936@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.2 Content-Transfer-Encoding: 8bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000037B6:EE_|CY1PR12MB9651:EE_ X-MS-Office365-Filtering-Correlation-Id: bf042c78-e5f5-41b0-af5b-08df39d6291f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|7416014|376014|23010399003|1800799024|6133799003|10067099003|18002099003|22082099003|921020|56012099006|11063799006|261021135927099003|261021121427099003|261028144727099003|261102123227099003|261026121527099003|261026140227099003|261021123027099003|261009223027099003|261022105027099003; X-Microsoft-Antispam-Message-Info: y6JwcLEaPoOtUyP06b4fHdyI09Sr8yNhsDQdwragJg0OiyE3Ps3++mai7l+ahQZA16eQ3L15G1k/Q/nZrjo0Q2dIFWVMObbLo4u/oFqw9XSzrSAWxJBpyXa9wfpIe3M8F1CmZ/qUe5WedGAEnsHNms2LGg97EMw27ulkVozR+N2IUsB1p/CxGdquC7y8AfsEAZKMz4KwMk015KTeDgSn+vjmNXD02JkF+SOXbPs+m1EE+/lVaeqJoyq/YNJDU4R0jXhYqhpxXrAa8Y/JDjhN5sQ6JtztbBMqXzG0LFV7J7Esz3y25WY+ml1jrnIxFgOxaywgcR0s9tIn0wpzqQzxrHaOGoyY2D9XPwUtZuBN+DF70nK9ddXBZAWV1fZ4wKa2f4hv8luS7pSMZ7BJ3dVQ8jB+hlOpB8NdrUeZAUsfyvdR808KmSIHfcHbsaYA/ApCCjsbJwLIkNJt/Tz2uCl8aoX9FBCFW3X7ggRxyYnjk2AzbBEMU+gcD3EeHoD8904/wVMlsZx4AeXR1CaiiUqHS9PsEuMn/BIMC4Jixi6HkGD2qGhftddfv8I2idqOYjFtFuocy7ft0tVXwke5EimMY1x1nxdVZaer40gf3GMoqrQ3EOQbBB8ElAqYjsL+mLocA5vFRDmGnybY7nLuvdEAnWOt1CvNCTcbR6WEiTkJxcIBQ9bO1gasIkTeKmZK2NTim7hDU8bpG61IrvcuympG5CoygDSnbcFFk6fBT2vf58xfc/bJOw9hdAbfwEVLvcTR X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(7416014)(376014)(23010399003)(1800799024)(6133799003)(10067099003)(18002099003)(22082099003)(921020)(56012099006)(11063799006)(261021135927099003)(261021121427099003)(261028144727099003)(261102123227099003)(261026121527099003)(261026140227099003)(261021123027099003)(261009223027099003)(261022105027099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LGjDQoDaM9v7e8U7c9gf2O1kVHw+nSNduQWktDDj5HmHSsdHOUELYdS1PJ0uzmV0g+E7vVsjvh3Lqld6BkNtfPjPnhbF5H9hThWbQW9/CZoUODtpH5Sa3H3gPjAi5kO2ImT+oMqIOageMVArG6eiwjm1DU0zp88hNuhp3s+YAa8gtZ5SlO/SiCIAOjbc4SRB7pdUtTv8aO0xlhd1qNuWSRxlJniUzonG9GVQuU2FATuc2eyD+N30DpQGApJUb4i8SW78uJvd7Q8TCyGCEvhbm74/4Crn2X+jzo9BzsQw8PAR89rXKNOEbkwszb574/o9W7ULbLTZ9AdEv2Cgm1a2aMPGzgAOy3jKen0MSxClVF3k3K+EKEiroezPfa5HqTCSB+h2kF21lv++LEp1kwywabAba6ViknhTxT+zwmJu53oy8hyjk4y9izalW0ItaKnK X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2026 18:13:28.5143 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf042c78-e5f5-41b0-af5b-08df39d6291f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000037B6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9651 From: Michael Gur Expose NIC_RX_CLASS capabilities in ADV_RDMA struct to allow exposing the new steering domain to users in the following patches. Signed-off-by: Michael Gur Reviewed-by: Mark Bloch Reviewed-by: Patrisious Haddad Signed-off-by: Edward Srouji --- include/linux/mlx5/mlx5_ifc.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 697fc9387b73ae1dd2305d475f7fdc767a1a2cdd..a7cf67264a1799ad179938907f5c871c9190f9e5 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -13690,7 +13690,14 @@ struct mlx5_ifc_adv_rdma_cap_bits { struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2; - u8 reserved_at_800[0x3800]; + u8 reserved_at_800[0x400]; + u8 reserved_at_c00[0x400]; + + struct mlx5_ifc_flow_table_prop_layout_bits nic_rx_class_flow_table_properties; + + u8 reserved_at_1200[0x500]; + + u8 reserved_at_1700[0x2900]; }; struct mlx5_ifc_adv_virtualization_cap_bits { -- 2.49.0