From: "Hongliang Yang (杨宏亮)" <hongliang.yang@cixtech.com>
To: "Vinod Koul" <vkoul@kernel.org>,
"Neil Armstrong" <neil.armstrong@linaro.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Gary Yang (杨新伟)" <Gary.Yang@cixtech.com>,
"Fugang Duan (段富刚)" <fugang.duan@cixtech.com>
Cc: "linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
cix-kernel-upstream <cix-kernel-upstream@cixtech.com>,
"Hongliang Yang (杨宏亮)" <hongliang.yang@cixtech.com>
Subject: [PATCH v5 0/3] phy: Add CIX Sky1 USB3 PHY support
Date: Tue, 3 Nov 2026 07:49:17 +0000 [thread overview]
Message-ID: <20261103074913.1971025-1-hongliang.yang@cixtech.com> (raw)
This series adds support for the USB3 PHY integrated in the CIX Sky1
SoC.
Patch 1 adds the device tree binding, patch 2 the PHY driver, and
patch 3 the SoC node plus the board enablement.
The PHY provides the SuperSpeed lanes for the Cadence USBSSP
controllers of the SoC. The block is multi-port: one instance is
exposed per controller port, and each instance handles its own reset
and clock management and the PIPE/PLL initialisation sequence.
Tested on Radxa Orion O6 (Sky1) together with the USBSSP controller
series: the PHY probes for both ports and USB 3.x devices enumerate at
SuperSpeed.
The controller device tree nodes use the PHY phandles added here; the
USBSSP controller series is posted separately.
The series applies on top of v7.4-rc1.
Changes since v4:
- Added the MAINTAINERS entries for the binding and the driver
directory.
- Documented the origin of the PHY initialization sequence.
- Return -ENODEV instead of -EINVAL when the OF match data is missing.
- Use dev_err_probe() when creating the child PHYs.
- Dropped the unused dev_set_drvdata() call.
- Guarded against underflow in sky1_u3phy_exit().
- Fixed the #size-cells property order and removed the unused phy.h
include and the redundant status properties of the PHY port nodes.
Hongliang Yang (3):
dt-bindings: phy: Add CIX Sky1 USB3 PHY
phy: cix: Add CIX Sky1 USB3 PHY driver
arm64: dts: cix: Add USB3 PHY nodes for Sky1
.../bindings/phy/cix,sky1-usb3-phy.yaml | 107 +++++
MAINTAINERS | 2 +
arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 4 +
arch/arm64/boot/dts/cix/sky1.dtsi | 25 ++
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/cix/Kconfig | 20 +
drivers/phy/cix/Makefile | 6 +
drivers/phy/cix/phy-cix-usb3.c | 418 ++++++++++++++++++
drivers/phy/cix/phy-cix-usbdp.h | 289 ++++++++++++
10 files changed, 873 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml
create mode 100644 drivers/phy/cix/Kconfig
create mode 100644 drivers/phy/cix/Makefile
create mode 100644 drivers/phy/cix/phy-cix-usb3.c
create mode 100644 drivers/phy/cix/phy-cix-usbdp.h
base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
--
2.54.0
next reply other threads:[~2026-11-03 7:49 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-03 7:49 Hongliang Yang (杨宏亮) [this message]
2026-11-03 7:49 ` [PATCH v5 1/3] dt-bindings: phy: Add CIX Sky1 USB3 PHY Hongliang Yang (杨宏亮)
2026-11-03 7:49 ` [PATCH v5 2/3] phy: cix: Add CIX Sky1 USB3 PHY driver Hongliang Yang (杨宏亮)
2026-11-03 8:44 ` Philipp Zabel
2026-11-03 7:49 ` [PATCH v5 3/3] arm64: dts: cix: Add USB3 PHY nodes for Sky1 Hongliang Yang (杨宏亮)
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