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Tue, 03 Nov 2026 02:16:44 -0800 (PST) Received: from arch-pc.genesyslogic.com.tw (2001-b400-e2d9-39f1-6373-5866-a392-6ad9.emome-ip6.hinet.net. [2001:b400:e2d9:39f1:6373:5866:a392:6ad9]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36a428af1easm40304226eec.5.2026.11.03.02.16.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 02:16:43 -0800 (PST) From: Ben Chuang To: adrian.hunter@intel.com, ulfh@kernel.org Cc: SeanHY.Chen@genesyslogic.com.tw, boris.chen@genesyslogic.com.tw, HL.Liu@genesyslogic.com.tw, benchuanggli@gmail.com, ben.chuang@genesyslogic.com.tw, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] mmc: sdhci-pci-gli: Add Genesys Logic GL9768 support Date: Tue, 3 Nov 2026 18:16:22 +0800 Message-ID: <20261103101622.213425-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.56.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Ben Chuang The GL9768 is the successor to the GL9767 and uses a compatible register layout. Reuse the GL9767 driver for the GL9768 by adding the GL9768 PCI device ID to the device ID table. Clear bits 2 and 3 in the SD Express control register at offset 0x940 when the driver initializes the device. This clears both bits to zero, matching the GL9767 default configuration. Signed-off-by: Ben Chuang --- drivers/mmc/host/sdhci-pci-core.c | 1 + drivers/mmc/host/sdhci-pci-gli.c | 7 +++++++ drivers/mmc/host/sdhci-pci.h | 1 + 3 files changed, 9 insertions(+) diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c index a9000f3bd419..db0417238131 100644 --- a/drivers/mmc/host/sdhci-pci-core.c +++ b/drivers/mmc/host/sdhci-pci-core.c @@ -1959,6 +1959,7 @@ static const struct pci_device_id pci_ids[] = { SDHCI_PCI_DEVICE(GLI, 9755, gl9755), SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e), SDHCI_PCI_DEVICE(GLI, 9767, gl9767), + SDHCI_PCI_DEVICE(GLI, 9768, gl9767), SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), /* Generic SD host controller */ {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c index b55618566d65..66452ed8cd8a 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -245,6 +245,8 @@ #define PCIE_GLI_9767_SD_EXPRESS_CTL 0x940 #define PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE BIT(0) #define PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE BIT(1) +#define PCIE_GLI_9767_SD_EXPRESS_CTL_DETECT_1 BIT(2) +#define PCIE_GLI_9767_SD_EXPRESS_CTL_DETECT_2 BIT(3) #define PCIE_GLI_9767_SD_DATA_MULTI_CTL 0x944 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 BIT(5) @@ -1354,6 +1356,11 @@ static void gl9767_hw_setting(struct sdhci_pci_slot *slot) PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF; pci_write_config_dword(pdev, PCIE_GLI_9767_SCR, value); + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value); + value &= ~(PCIE_GLI_9767_SD_EXPRESS_CTL_DETECT_1 | + PCIE_GLI_9767_SD_EXPRESS_CTL_DETECT_2); + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value); + gl9767_vhs_read(pdev); } diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h index f38f0bd4165c..bcae29f8d8da 100644 --- a/drivers/mmc/host/sdhci-pci.h +++ b/drivers/mmc/host/sdhci-pci.h @@ -81,6 +81,7 @@ #define PCI_DEVICE_ID_GLI_9750 0x9750 #define PCI_DEVICE_ID_GLI_9763E 0xe763 #define PCI_DEVICE_ID_GLI_9767 0x9767 +#define PCI_DEVICE_ID_GLI_9768 0x9768 /* * PCI device class and mask base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4 -- 2.56.0