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Signed-off-by: Changhuang Liang Reviewed-by: Rob Herring (Arm) --- .../pinctrl/starfive,jhb100-emmc-pinctrl.yaml | 129 ++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-emmc-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-emmc-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-emmc-pinctrl.yaml new file mode 100644 index 000000000000..4533209d9965 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-emmc-pinctrl.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-emmc-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 eMMC Pin Controller + +description: | + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd. + + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1, + per2, per2pok, per3, adc0, adc1, emmc, and vga. + This document provides an overview of the "emmc" pinctrl domain. + + The "emmc" domain has a pin controller which provides + - function selection for GPIO pads. + - GPIO pad configuration. + - GPIO interrupt handling. + + In the eMMC Pin Controller, there are 12 multi-function GPIO_PADs. Each of + them can be multiplexed to several peripherals through function selection. + Each iopad has a maximum of up to 2 functions - 0 and 1. Function 0 + is the default function which is generally the GPIO function. Function 1 + is the alternate functions or peripheral signals that can be routed to an + iopad. The function selection can be carried out by writing the function + number to the iopad function select register. + + Each iopad is configurable with parameters such as input debounce + nanoseconds. + +maintainers: + - Changhuang Liang + +properties: + compatible: + items: + - const: starfive,jhb100-emmc-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: true + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + function selection and input debounce. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pins: + description: + The list of IOs that properties in the pincfg node apply to. + + function: + description: + A string containing the name of the function to mux for these + pins. + enum: [ emmc, gpio ] + + input-debounce-ns: + minimum: 0 + maximum: 10485680 + description: + Debounce time in nanoseconds. The hardware counts in 80 ns + stages with a 17-bit counter, so the maximum is 10485680 ns. + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_emmc: pinctrl@11b42800 { + compatible = "starfive,jhb100-emmc-pinctrl"; + reg = <0x0 0x11b42800 0x0 0x800>; + interrupts = <119>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_emmc 0 0 12>; + }; + }; -- 2.25.1