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([179.179.238.247]) by smtp.gmail.com with ESMTPSA id ada2fe7eead31-7d0775a716dsm12606282137.6.2026.11.03.04.12.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 04:12:11 -0800 (PST) From: Vinicius Pedrosa To: Andre Przywara Cc: Junhui Liu , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, Jerome Brunet , Enzo Adriano , Norman Herms Subject: Re: [PATCH v6 6/8] clk: sunxi-ng: a733: Add mod clocks support Date: Tue, 3 Nov 2026 09:11:49 -0300 Message-ID: <20261103121149.33238-1-vinicius.eduardo.pedrosa@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <30e43e84-e6e8-4024-b415-dedf67070c4f@arm.com> References: <20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech> <20261009-a733-clk-v6-6-ae8178fce7e8@pigmoral.tech> <30e43e84-e6e8-4024-b415-dedf67070c4f@arm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi Andre, On 11/2/26 16:32, Andre Przywara wrote: [...] > > +static const struct clk_parent_data usb01_ref_parents[] = { > > + { .hw = &sys_24M_clk.hw }, > > + { .fw_name = "hosc" }, > > +}; > > +static SUNXI_CCU_MUX_DATA(usb01_ref_clk, "usb01-ref", usb01_ref_parents, 0x1340, 24, 3, 0); > > + > > +static SUNXI_CCU_MUX_DATA(usb2_u2_ref_clk, "usb2-u2-ref", usb01_ref_parents, 0x1348, 24, 3, 0); > > Don't these two clocks miss the gate at bit 31? So it should be > SUNXI_CCU_MUX_DATA_WITH_GATE instead? Yes, both have the gate at bit 31 in the manual, and the vendor CCU models 0x1340 with it too. usb2-u2-ref resets to off, which is the one I hit on my board. usb01-ref resets to on, so nothing breaks today. With the gate added, clk_disable_unused would switch usb01-ref off unless something claims it, and in my local DT nothing does (the USB0/USB1 PHYs take osc24M like the A523 ones). On my Cubie A7Z, clearing bit 31 of 0x1340 at runtime stops the USB1 Wi-Fi traffic, and after rebinding EHCI1/OHCI1 the device no longer enumerates (error -62), 4 out of 4, while it enumerates again with the bit set. So at least USB1 will need CLK_USB01_REF kept enabled once the gate is added, likely through a consumer in the USB controller or PHY, as suggested by the vendor DT. I only tested USB1, by writing the register, not the gated CCU itself. Thanks also for your guidance throughout these discussions. Thanks, Vinicius