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Bottomley" , "Martin K. Petersen" , Sai Krishna Potthuri , Ajay Neeli , Manivannan Sadhasivam , Pedro Sousa , Adrian Hunter , Can Guo , Asutosh Das Cc: imx@lists.linux.dev, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, clizzi@redhat.com, aruizrui@redhat.com, eballetb@redhat.com, echanude@redhat.com, Frank Li Subject: [PATCH v10 08/11] dt-bindings: ufs: Add NXP S32N79 UFS host controller Date: Tue, 3 Nov 2026 14:32:12 +0100 Message-ID: <20261103133215.1385823-9-larisa.grigore@oss.nxp.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261103133215.1385823-1-larisa.grigore@oss.nxp.com> References: <20261103133215.1385823-1-larisa.grigore@oss.nxp.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: AS9PR06CA0532.eurprd06.prod.outlook.com (2603:10a6:20b:49d::31) To GV2PR04MB12558.eurprd04.prod.outlook.com (2603:10a6:150:368::10) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV2PR04MB12558:EE_|GVXPR04MB704257:EE_ X-MS-Office365-Filtering-Correlation-Id: 477f5a64-23d1-4222-34b6-08df39aef7c9 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|19092799006|376014|7416014|1800799024|23010399003|366016|3023799007|10067099003|22082099003|261102123227099003|18002099003|56012099006|11063799006|261022075727099003|921020|261022105027099003|261026121527099003|261026140227099003|261028144727099003|261009223027099003|261021121427099003; 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The S32N79 M-PHY has two data lanes per direction and the driver programs both of them, so restrict lanes-per-direction to 2. The UFS core manages only the clocks added by the platform glue. Since freq-table-hz is deprecated, the binding requires operating-points-v2 and clock-names. As S32N79 does not scale the UFS clock, the OPP table contains a single 0 Hz entry, which keeps the provider-configured rate while allowing the clock to be enabled and gated. Reviewed-by: Frank Li Signed-off-by: Larisa Grigore --- .../bindings/ufs/nxp,s32n79-ufshc.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/ufs/nxp,s32n79-ufshc.yaml diff --git a/Documentation/devicetree/bindings/ufs/nxp,s32n79-ufshc.yaml b/Documentation/devicetree/bindings/ufs/nxp,s32n79-ufshc.yaml new file mode 100644 index 000000000000..541b59b8c89a --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/nxp,s32n79-ufshc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/nxp,s32n79-ufshc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32N79 Universal Flash Storage (UFS) Controller + +maintainers: + - Larisa Grigore + +properties: + compatible: + const: nxp,s32n79-ufshc + + reg: + items: + - description: UFS Host Controller registers + - description: System Control Module registers + + reg-names: + items: + - const: ufshc + - const: scm + + clocks: + maxItems: 1 + + clock-names: + items: + - const: core + + lanes-per-direction: + const: 2 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - operating-points-v2 + +allOf: + - $ref: ufs-common.yaml + +unevaluatedProperties: false + +examples: + - | + ufshc@4ac80000 { + compatible = "nxp,s32n79-ufshc"; + reg = <0x4ac80000 0x1000>, <0x4ac40000 0x1000>; + reg-names = "ufshc", "scm"; + interrupt-parent = <&irqsteer_coss>; + interrupts = <211>; + clocks = <&clks 0x92>; + clock-names = "core"; + operating-points-v2 = <&ufs_opp_table>; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-hz = /bits/ 64 <0>; + }; + }; + }; -- 2.43.0