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Tue, 3 Nov 2026 09:12:45 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.2562.56 via Frontend Transport; Tue, 3 Nov 2026 09:12:41 -0800 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Akiva Goldberger , Carolina Jubran , Cosmin Ratiu , Edward Srouji , Gal Pressman , Leon Romanovsky , open list , , Mark Bloch , Moshe Shemesh , Or Har-Toov , Patrisious Haddad , Saeed Mahameed , Shay Drory , Tariq Toukan Subject: [PATCH net-next 11/15] net/mlx5: E-switch, add match-metadata allocator for nested VF/SF eswitches Date: Tue, 3 Nov 2026 19:10:05 +0200 Message-ID: <20261103171009.563034-12-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20261103171009.563034-1-tariqt@nvidia.com> References: <20261103171009.563034-1-tariqt@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PEPF000265B3:EE_|DS6PR12MB262455:EE_ X-MS-Office365-Filtering-Correlation-Id: ec823538-daf3-430a-77ef-08df39cdc28d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|1800799024|23010399003|6133799003|10067099003|18002099003|22082099003|261102123227099003|56012099006|11063799006|5023799004|261022105027099003|261026121527099003|261026140227099003|261028144727099003|261009223027099003|261102130727099003|261021121427099003; X-Microsoft-Antispam-Message-Info: h0dZ7BltJck5ZyGz+Jo7mf0/gP5nqcaU1ZTck0st/El6QGJaohCuvu4jQyaYPIWX7+xtua8QOoAH1gJ6C0rqE4geM2qOi6CTnF4e2P8R9sGMbltYKVPDGGIMYQiXB5Cg1jT49eN9SK1TVPWUDAPw+xpSgTZwYKzWXpRl7ke0Eqqk/5tOhiYgHu+zip32CLb+GJ4M0P0ESjcs11/kJs8M5uPTAdjy8OjbaW13zbNvbchOx9RoFP/i9B6yDG4fNS8RetfWEB0bBkT7FH1WGndqC0Vaau1Uy2j1gxYPnRsuUp1yCcwq3mipPwITKjWNVydODOTlU67iECp5FSjQF26WhATd5t8kdtdPhgTChWRBrdIfol2riVF498NzMtyoJq+0HcusfR8MKJ/hRuZqmvPUp+DH5l63iPwmpVJ0q4+jauaGaA/0UWOyoRbZrO6I2ggyjVYpNd37wzwS4qipsT1G4AdBcy84Y+OVaMKsNcPM78UgGMEDT+kS4ioKWClCE8b/pN4CYKMNl/rVYYb0L5KD7i0LJLRuBW/5rvzlEOgFgZwkrgF9Sf6MeW9WA9r/m415FC6N882kE+JgfRqH2JQPbOOzQuQ2LT0Ab5Aw+M4m6BAGDtngpzqsLlwASesKmv8HkhAkT16e7zoBlPG9RElwCBwbikPp6s2mrR4NVyjYwLOSqA9j43X7TzqHG5pFY/v2VyVREo6Am4Nv5xVCtm1yvw== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(376014)(1800799024)(23010399003)(6133799003)(10067099003)(18002099003)(22082099003)(261102123227099003)(56012099006)(11063799006)(5023799004)(261022105027099003)(261026121527099003)(261026140227099003)(261028144727099003)(261009223027099003)(261102130727099003)(261021121427099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HfyRNB0RrLHbcjhiRyjSi6d8a/Z2i23uU0l56t6e6b+YDafJoih7T4zLta9GEI/7REMuPvtK68aLid98F4WA0iuDBL5wCVVpUOwE8jIkKeYWc7XSgbdsrMXFJAREGPBTA7dmTo1OfywXzXgdPNIdTSbsoZovUgDUpHJbbu58kPeOWYLLuSGT0KEWxv/a3vxJC7FdBa7x0iGuDoR7Usi52yf6sDbRI4l60Cel2D4xQdF/+1KBGl9pMlr3zjDO0uWB0vjcb7wnbNEvHJyZ9L8MIhG9ayfckiqH6PCFdFvIJAS1sJeEiEWQ46Fh9FEsdzAeBwQnBL5BdySm9HTaIY4Hcy+ceMKasSdx8UIsq9uHb1fuw1iFm/gi6P67hOC6u647oj5XcoPb5G+sjjAfmkBKtH6eo5LsScBcG9nBuydICLtghqWhfOIhh1TySTReN0Fu X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2026 17:13:20.3571 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ec823538-daf3-430a-77ef-08df39cdc28d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM3PEPF000265B3.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS6PR12MB262455 From: Shay Drory The eswitch source-port match metadata is laid out as 4 bits of PFNUM and 12 bits of a unique id (ESW_SOURCE_PORT_METADATA_BITS). PFNUM is the native_port_num reported in HCA_CAP, so all VFs/SFs of the same PF share a single PFNUM. Each VF/SF eswitch allocates its id from its own vport_metadata_ida, restarting from the lowest value, so two VFs/SFs of the same PF can end up with identical metadata. Once their eswitches share an FDB (virt LAG), that metadata no longer uniquely identifies the source port. Add a dedicated allocator for nested (virt LAG) eswitches that replaces the PFNUM field with the VF/SF's slot in the LAG (its xarray index in ldev->fns). That index is unique per function within the LAG, so combined with a per-VF/SF id it yields unique metadata regardless of which PF the VFs/SFs belong to. The split is 8 bits for the virt LAG index - which fits the U8_MAX cap on the LAG xarray - and the remaining 8 bits for the id; the two still sum to ESW_SOURCE_PORT_METADATA_BITS, so nothing downstream of the match changes. The PFNUM value 0xf is reserved for internal port offload, which stamps it into reg_c_0 and matches it with the same mask used for vport metadata. That offload is gated on switchdev mode only, so it can be used on a nested eswitch as well. Cap the LAG index accordingly. Select the nested layout for any non-PF eswitch, so every PF keeps the PFNUM layout regardless of its virt LAG capabilities. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Reviewed-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/eswitch_offloads.c | 48 +++++++++++++++++++ .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 17 +++++++ .../ethernet/mellanox/mlx5/core/mlx5_core.h | 1 + 3 files changed, 66 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 70e6dd9561a6..ef1043517e9e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3651,6 +3651,48 @@ static u32 mlx5_esw_match_metadata_reserved(struct mlx5_eswitch *esw) return MLX5_ESW_METADATA_RSVD_UPLINK; } +/* Nested (virt LAG) source-port metadata layout: the upper ESW_NESTED_IDX_BITS + * hold the VF/SF's slot in the LAG and the lower ESW_NESTED_VPORT_BITS hold a + * vport id unique within its eswitch. The two fields still sum to + * ESW_SOURCE_PORT_METADATA_BITS. The LAG slot (0-254, per the xa_alloc() limit + * in mlx5_ldev_add_mdev()) fits in ESW_NESTED_IDX_BITS; slots 0xf0 and up would + * drive the PFNUM bits to the 0xf reserved by internal port offload, so only + * 0-239 are used. + */ +#define ESW_NESTED_VPORT_BITS 8 +#define ESW_NESTED_IDX_BITS (ESW_SOURCE_PORT_METADATA_BITS - ESW_NESTED_VPORT_BITS) + +static u32 mlx5_nested_esw_match_metadata_alloc(struct mlx5_eswitch *esw) +{ + u32 vport_end_ida = (1 << ESW_NESTED_VPORT_BITS) - 1; + u32 max_idx = (1 << ESW_NESTED_IDX_BITS) - + (1 << (ESW_NESTED_IDX_BITS - ESW_PFNUM_BITS)) - 1; + int idx; + int id; + + idx = mlx5_lag_get_member_idx(esw->dev); + if (idx < 0 || idx > max_idx) + return 0; + + /* Use only non-zero id's (2-255). */ + id = ida_alloc_range(&esw->offloads.vport_metadata_ida, + MLX5_ESW_METADATA_RSVD_UPLINK + 1, + vport_end_ida, GFP_KERNEL); + if (id < 0) + return 0; + id = (idx << ESW_NESTED_VPORT_BITS) | id; + return id; +} + +static void mlx5_nested_esw_match_metadata_free(struct mlx5_eswitch *esw, + u32 metadata) +{ + u32 vport_bit_mask = (1 << ESW_NESTED_VPORT_BITS) - 1; + + /* Metadata holds only ESW_NESTED_VPORT_BITS of actual ida id. */ + ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask); +} + u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw) { u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1; @@ -3659,6 +3701,9 @@ u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw) int pf_num; int id; + if (!mlx5_core_is_pf(esw->dev) && !mlx5_virt_lag_nonmember(esw->dev)) + return mlx5_nested_esw_match_metadata_alloc(esw); + /* Only 4 bits of pf_num */ pf_num = mlx5_sd_pf_num_get(esw->dev); if (pf_num < 0 || pf_num > max_pf_num) @@ -3679,6 +3724,9 @@ void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata) { u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1; + if (!mlx5_core_is_pf(esw->dev) && !mlx5_virt_lag_nonmember(esw->dev)) + return mlx5_nested_esw_match_metadata_free(esw, metadata); + /* Metadata contains only 12 bits of actual ida id */ ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask); } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c index d73bac8441f7..4e15e16ae6e8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -516,6 +516,23 @@ int mlx5_lag_get_dev_seq(struct mlx5_core_dev *dev) } EXPORT_SYMBOL(mlx5_lag_get_dev_seq); +int mlx5_lag_get_member_idx(struct mlx5_core_dev *dev) +{ + struct mlx5_lag *ldev = mlx5_lag_dev(dev); + struct lag_fn *fn; + int idx; + + if (!ldev) + return -ENOENT; + + xa_lock(&ldev->fns); + fn = mlx5_lag_fn_by_dev(ldev, dev); + idx = fn ? fn->idx : -ENOENT; + xa_unlock(&ldev->fns); + + return idx; +} + /* seq 0 = master, then all remaining devices */ static int mlx5_lag_get_dev_index_by_seq_all(struct mlx5_lag *ldev, int seq) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h index d84d0424d04e..f5f105762d88 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -275,6 +275,7 @@ void mlx5_lag_add_mdev(struct mlx5_core_dev *dev); void mlx5_lag_remove_mdev(struct mlx5_core_dev *dev); void mlx5_lag_disable_change(struct mlx5_core_dev *dev); void mlx5_lag_enable_change(struct mlx5_core_dev *dev); +int mlx5_lag_get_member_idx(struct mlx5_core_dev *dev); int mlx5_events_init(struct mlx5_core_dev *dev); void mlx5_events_cleanup(struct mlx5_core_dev *dev); -- 2.44.0