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Tue, 3 Nov 2026 09:12:56 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.2562.56 via Frontend Transport; Tue, 3 Nov 2026 09:12:51 -0800 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Akiva Goldberger , Carolina Jubran , Cosmin Ratiu , Edward Srouji , Gal Pressman , Leon Romanovsky , open list , , Mark Bloch , Moshe Shemesh , Or Har-Toov , Patrisious Haddad , Saeed Mahameed , Shay Drory , Tariq Toukan Subject: [PATCH net-next 13/15] net/mlx5: E-switch, drop master egress rule under a SW vport LAG Date: Tue, 3 Nov 2026 19:10:07 +0200 Message-ID: <20261103171009.563034-14-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20261103171009.563034-1-tariqt@nvidia.com> References: <20261103171009.563034-1-tariqt@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PEPF000265AF:EE_|PH7PR12MB9076:EE_ X-MS-Office365-Filtering-Correlation-Id: 9ed2e413-8175-454d-fe86-08df39cdc648 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|23010399003|376014|36860700016|82310400026|11063799006|261022105027099003|56012099006|261009223027099003|261021121427099003|261021123027099003|261102123227099003|261028144727099003|261026121527099003|261026140227099003|10067099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: fLEsWbATjjxjdijoSJLsKDsTnEG+Z3DPobd1jwXSlekzKsf50+9o23QT9W0fT+Uqg1di72dmYKi2YYr3+ESaBCuoJ1eccGMqrhaB8v8svDE5CPM35wIKPbS4cMTrrxOTSlxMaaEA2CvcIHjjyQLE/k9lM3j/a/wxp9lVO1ssjWFM3TfD6K4zKQOE1wh7bspNqAze2A0IYK3mjirORQWDjeqfKlYvodRFknXaIJZRP3UYzC45HArGd61eWYSgtpK5yzGZ2lMoOi/ZZLvDiJRTAuWOqPepuahiwVSVLtJYvx8sBUW6QFNaKocdmfXdmU5V22PFCnDBJFXGegUaFoJM6O2xZ5In/1USpiDmJe6Xj7x18l5atHgVr/BNCnwZQgBen7n50FCf/SBT6F9EORIuBy1UFuWK0doaMy1oErhsfSLxqF4TfY9v3DP4dAPCTeTbNOyYZpV6dNgLGSFKzjCoU2oCwM81Isfl9/2XKyMZeWHIZj8wcSeDnOmvAw4JVpC+ieMGgeXKYNAGOX4q5BqfmUxH6DMNZongZYZ1wvPDWMrBTdfLjmnST+i+DRe+s6HFhVEECDNk2uzOVrs4TjmCqriMq6KhI55lu0/NBqed1/wLtHL+HCmdfMknJuNgTAVlrK1qdXRDagy6eBGCbH6EtGfujYgJqQYSPNMeRPZo42Q4W9hX2MTMjj52I6HGK6EXr1woOb7r1xsofI7UiRkUIw== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(23010399003)(376014)(36860700016)(82310400026)(11063799006)(261022105027099003)(56012099006)(261009223027099003)(261021121427099003)(261021123027099003)(261102123227099003)(261028144727099003)(261026121527099003)(261026140227099003)(10067099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Cv0ZN/zPF2VPc2Rl0CmFwcYiulfRqMnIZcahoeSPvNFm0BiObTU8BEPe3kIMXLZHF7ILjj3w78rhNk7/8x9fzBnxujj+yseGc7F/UXRoag1gF2pJgLEPp0I0Uv6f2Vuw5acNyzVfj+NvOP40nJFgsyCT2XcEsnAT0Ti+jkP4NemeViRAfyVzAh+zMPldLECQOVqTJuf1gfd2VMjxZbgRL1wrZpC/jz2hmfoLu0k/VFBgA50jsp8WtZZIxYkLR3CQWnEczRcCp5B9zFqsAkPN38MTbiOv34xoTzQUW9jSpTDEx0M/0bbvl6q4X3MQD7Im8TWPDfmQVrN7FWtc0S6PxjBXEuIXJAWPR/htIRxwRDlBkbhpVTfCIGHCf8wv2Lt5739HTWAPexb1utYN0VlkrTapxD8ktRmuXyHfE8e5I/HUtv4/jd4kNPA1P+az/mvZ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2026 17:13:26.6539 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ed2e413-8175-454d-fe86-08df39cdc648 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM3PEPF000265AF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9076 From: Shay Drory VPORT_LAG steers all traffic of a LAG slave to the LAG master. The eswitch master egress rule does the opposite direction: it bounces traffic that reached the master's manager vport into the slave eswitch. With a FW vport LAG the FW steers that bounced packet to the LAG master, so the two coexist. The software vport LAG emulation cannot. It is a catch-all rule in the slave eswitch's egress ACL that forwards to the master's manager vport, while the master egress rule redirects the packet after the FDB - past the point where the slave egress rule is evaluated - so the bounced packet never reaches it. The two therefore cannot coexist: drop the master egress rule when the software vport LAG is installed, and restore it when it is removed. Both rules are keyed by the peer vhca_id, so each slave swaps its own pair independently. Restoring needs the ACL size, so pass ldev->max_funcs down to mlx5_eswitch_offloads_vport_lag_del_one(), as the single FDB path already does. Also, release the MPESW metadata after the shared FDB is destroyed, mirroring the creation order. Releasing it first makes all slaves fall back to the same default uplink metadata, so the restored master egress rules collide. Note that vport LAG on its own only gets traffic to the LAG master; the distribution to the other slaves esw managers, which was managed by master egress rules, is done by the LAG demux Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Reviewed-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 3 ++- .../mellanox/mlx5/core/eswitch_offloads.c | 24 +++++++++++++++++-- .../ethernet/mellanox/mlx5/core/lag/mpesw.c | 2 +- .../mellanox/mlx5/core/lag/shared_fdb.c | 6 +++-- 4 files changed, 29 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h index e9cbcd73b23f..55f5ea522d46 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -957,7 +957,8 @@ bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 cont int mlx5_eswitch_offloads_vport_lag_add_one(struct mlx5_eswitch *master_esw, struct mlx5_eswitch *slave_esw); void mlx5_eswitch_offloads_vport_lag_del_one(struct mlx5_eswitch *master_esw, - struct mlx5_eswitch *slave_esw); + struct mlx5_eswitch *slave_esw, + int max_slaves); int mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_esw, struct mlx5_eswitch *slave_esw, int max_slaves); void mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index d633c63b309b..f1a5d7d036cb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3381,12 +3381,32 @@ void mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw, int mlx5_eswitch_offloads_vport_lag_add_one(struct mlx5_eswitch *master_esw, struct mlx5_eswitch *slave_esw) { - return esw_set_slave_egress_rule(master_esw->dev, slave_esw->dev); + int err; + + err = esw_set_slave_egress_rule(master_esw->dev, slave_esw->dev); + if (err) + return err; + + esw_unset_master_egress_rule(master_esw->dev, slave_esw->dev); + + return 0; } void mlx5_eswitch_offloads_vport_lag_del_one(struct mlx5_eswitch *master_esw, - struct mlx5_eswitch *slave_esw) + struct mlx5_eswitch *slave_esw, + int max_slaves) { + int err; + + if (mlx5_sd_is_primary(slave_esw->dev)) { + err = esw_set_master_egress_rule(master_esw->dev, + slave_esw->dev, max_slaves); + if (err) + esw_warn(master_esw->dev, + "Failed to restore master egress rule (%d)\n", + err); + } + esw_unset_slave_egress_rule(master_esw->dev, slave_esw->dev); } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c index 584436668a5c..3dd7fa8de66c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c @@ -208,10 +208,10 @@ void mlx5_lag_disable_mpesw(struct mlx5_lag *ldev) if (ldev->mode != MLX5_LAG_MODE_MPESW) return; - mlx5_mpesw_metadata_cleanup(ldev); mlx5_lag_shared_fdb_destroy(ldev, MLX5_LAG_FILTER_ALL); if (mlx5_lag_has_sd_group(ldev)) mlx5_mpesw_restore_sd_fdb(ldev); + mlx5_mpesw_metadata_cleanup(ldev); /* Pair with the master mark taken at MPESW create for VFs. */ if (ldev->virt_lag) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c index 404278a15ef7..90209e4b99f7 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c @@ -126,7 +126,8 @@ int mlx5_lag_create_vport_lag(struct mlx5_lag *ldev, u32 group_id) if (j == master_idx) continue; slave_esw = mlx5_lag_fn(ldev, j)->dev->priv.eswitch; - mlx5_eswitch_offloads_vport_lag_del_one(master_esw, slave_esw); + mlx5_eswitch_offloads_vport_lag_del_one(master_esw, slave_esw, + ldev->max_fns); } return err; } @@ -153,7 +154,8 @@ int mlx5_lag_destroy_vport_lag(struct mlx5_lag *ldev, u32 group_id) continue; dev = mlx5_lag_fn(ldev, i)->dev; mlx5_eswitch_offloads_vport_lag_del_one(master_esw, - dev->priv.eswitch); + dev->priv.eswitch, + ldev->max_fns); } return 0; } -- 2.44.0