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Tue, 03 Nov 2026 11:23:40 -0800 (PST) Received: from neuromancer ([75.28.21.198]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-85ef3e16ef1sm43323a34.14.2026.11.03.11.23.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 11:23:39 -0800 (PST) From: Chris Morgan To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, david@ixit.cz, detlev.casanova@collabora.com, maz@kernel.org, michael.riesch@collabora.com, diederik@cknow-tech.com, shawn.lin@rock-chips.com, heiko@sntech.de, conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org, tglx@kernel.org, daniel.lezcano@kernel.org, Chris Morgan Subject: [PATCH 2/2] arm64: dts: rockchip: Add timer node for rk356x Date: Tue, 3 Nov 2026 13:23:31 -0600 Message-ID: <20261103192331.394489-3-macroalpha82@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261103192331.394489-1-macroalpha82@gmail.com> References: <20261103192331.394489-1-macroalpha82@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Chris Morgan Add the timer node for the rk356x. The timer is present at the SoC level and is register compatible with the rk3288 timer. Signed-off-by: Chris Morgan --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 1a4562df20ee..cc3faeb9a86d 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -1373,6 +1373,14 @@ i2c5: i2c@fe5e0000 { status = "disabled"; }; + timer0: timer@fe5f0000 { + compatible = "rockchip,rk3568-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xfe5f0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; + clock-names = "pclk", "timer"; + }; + wdt: watchdog@fe600000 { compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; reg = <0x0 0xfe600000 0x0 0x100>; -- 2.53.0