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[93.34.90.148]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4b43457595asm1140405e9.4.2026.11.03.12.55.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 12:55:11 -0800 (PST) From: Christian Marangi To: Stephen Boyd , Brian Masney , Jerome Brunet , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v2 1/2] clk: en7523: convert to full clk_hw implementation for en7581 Date: Tue, 3 Nov 2026 21:54:19 +0100 Message-ID: <20261103205500.14974-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261103205500.14974-1-ansuelsmth@gmail.com> References: <20261103205500.14974-1-ansuelsmth@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit In preparation for support of .set_rate, convert the clock register logic from fixed clock implementation to full clk_hw implementation with dedicated OPs for Airoha EN7581 SoC. This is just a rework and no behaviour change is expected. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 86 +++++++++++++++++++++++++++++----------- 1 file changed, 62 insertions(+), 24 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 24fdec2e6198..aab4306ae037 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -126,6 +126,12 @@ struct en_clk_gate { struct clk_hw hw; }; +struct en_clk { + struct regmap *map; + const struct en_clk_desc *desc; + struct clk_hw hw; +}; + struct en_rst_data { const u16 *bank_ofs; const u16 *idx_map; @@ -742,46 +748,76 @@ static int en7523_clk_hw_init(struct platform_device *pdev, en7581_rst_ofs); } -static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, - struct regmap *map, void __iomem *base) +static unsigned long en7581_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) { - struct clk_hw *hw; + struct en_clk *c = container_of(hw, struct en_clk, hw); + const struct en_clk_desc *desc = c->desc; + struct regmap *map = c->map; + u32 val, reg; u32 rate; + int err; + + err = regmap_read(map, desc->base_reg, &val); + if (err) { + pr_err("Failed reading fixed clk rate %s: %d\n", + desc->name, err); + return 0; + } + rate = en7523_get_base_rate(desc, val); + + reg = desc->div_reg ? desc->div_reg : desc->base_reg; + err = regmap_read(map, reg, &val); + if (err) { + pr_err("Failed reading fixed clk div %s: %d\n", + desc->name, err); + return 0; + } + + return rate / en7523_get_div(desc, val); +} + +static const struct clk_ops en7581_clk_ops = { + .recalc_rate = en7581_recalc_rate, +}; + +static int en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, + struct regmap *map, void __iomem *base) +{ + struct clk_hw *hw; int i; for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) { const struct en_clk_desc *desc = &en7581_base_clks[i]; - u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg; + struct clk_init_data init = { + .ops = &en7581_clk_ops, + }; + struct en_clk *en_clk; int err; - err = regmap_read(map, desc->base_reg, &val); - if (err) { - pr_err("Failed reading fixed clk rate %s: %d\n", - desc->name, err); - continue; - } - rate = en7523_get_base_rate(desc, val); + en_clk = devm_kzalloc(dev, sizeof(*en_clk), GFP_KERNEL); + if (!en_clk) + return -ENOMEM; - err = regmap_read(map, reg, &val); + init.name = desc->name; + en_clk->map = map; + en_clk->desc = desc; + en_clk->hw.init = &init; + + err = devm_clk_hw_register(dev, &en_clk->hw); if (err) { - pr_err("Failed reading fixed clk div %s: %d\n", + pr_err("Failed to register clk %s: %d\n", desc->name, err); - continue; + return err; } - rate /= en7523_get_div(desc, val); - hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %ld\n", - desc->name, PTR_ERR(hw)); - continue; - } - - clk_data->hws[desc->id] = hw; + clk_data->hws[desc->id] = &en_clk->hw; } hw = en7523_register_pcie_clk(dev, base); clk_data->hws[EN7523_CLK_PCIE] = hw; + + return 0; } static int en7523_reset_update(struct reset_controller_dev *rcdev, @@ -1062,7 +1098,9 @@ static int en7581_clk_hw_init(struct platform_device *pdev, priv->base = base; - en7581_register_clocks(&pdev->dev, clk_data, map, base); + ret = en7581_register_clocks(&pdev->dev, clk_data, map, base); + if (ret) + return ret; val = readl(base + REG_NP_SCU_SSTR); val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); -- 2.55.0