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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b245c1c272sm1537440c88.8.2026.11.03.13.41.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 13:41:08 -0800 (PST) From: Anusha Arun Nandi To: Bryan O'Donoghue Cc: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , gjorgji.rosikopulos@oss.qualcomm.com, hariram.purushothaman@oss.qualcomm.com, akapatra@quicinc.com, jigarkumar.zala@oss.qualcomm.com, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/5] phy: qcom-mipi-csi2: Make timer and OPP clock names configurable Date: Tue, 3 Nov 2026 13:41:02 -0800 Message-Id: <20261103214105.3605181-3-anusha.nandi@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261103214105.3605181-1-anusha.nandi@oss.qualcomm.com> References: <20261103214105.3605181-1-anusha.nandi@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMTAzMDA4NiBTYWx0ZWRfX+hGvdSbuQ3Uw Z6zWK15THwuQ3LDFUt2GDdlEBK5PITzz5WWEWNm1K4NYW6Pk2DwfMPPKu01S7lY6xC6F7EXbYnr Ii4nUnaYV7ykwUR3M+wAY8Euor9FqSc= X-Authority-Analysis: v=2.4 cv=AKV9GsJK c=1 sm=1 tr=0 ts=6aea54f5 cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=YDrJLkQi9lszU93BSgcA:9 a=Fk4IpSoW4aLDllm1B1p-:22 X-Proofpoint-ORIG-GUID: B2jzRTS0qYshumYNmOvMaFLGd6PrE960 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTAzMDA4NiBTYWx0ZWRfXzFTXX+N3KVzZ 4fzy+tF4gxr8vZudiSJm46FtLfG5AfZrOsK+fjxMNETTEDcAUhQBvJSkh3pf4O5Yt6z5QbvRKBm 4Svt8d5/5UvmyF1YeqBMub7UYOXz1eWO1ET1IwTfLbJe1m0NMrHf2j66B9EUl7pBVJQLaeyuSRp brDJXMo8Fl9oFmkGe2lPEYeaRFt9OTNRdXrLdwRHnHpRzOIU7pgK/43VqZlvxeSVwsRkgEoIxd+ v7+NOSDmXHMkr1MmsTu6S22F6dUSemfsu51JXv4+GnC2bnXyxzRjT/cMpYkwEIxpUK4VHnd/azS OVVcMrOay7IRDQXgSFIGxub7SCDwVhj/Z/2dHpK3CUNAqOw9+yDxhcx3skqeg6WPh8cp6mtorUY PNwmkLK3iEUFiw8BvSmqb3cSUG5GaHezCg2EXHBqedtZMJnCaXIR6u1ZUxsUVX2RdPbMYJNgRQ7 99BU9yoqAb+293A6cGw== X-Proofpoint-GUID: B2jzRTS0qYshumYNmOvMaFLGd6PrE960 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-03_05,2026-11-03_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 bulkscore=0 suspectscore=0 impostorscore=0 phishscore=0 spamscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611030086 The timer-clock lookup in phy_qcom_mipi_csi2_probe() and the OPP clkname passed to devm_pm_opp_set_clkname() were both hardcoded string literals sized to x1e80100 ("timer"/"core"). Add timer_clk_name/opp_clk_name to struct mipi_csi2phy_soc_cfg so each SoC can declare its own clock-name strings instead. x1e80100's soc_cfg now declares "timer"/"core" explicitly; no behaviour change. Reviewed-by: Jigarkumar Zala Signed-off-by: Anusha Arun Nandi --- drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 2 ++ drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c | 4 ++-- drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 3 +++ 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c index 966d79c98f9b..8f1939e81e13 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c @@ -380,6 +380,8 @@ const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e = { .num_supplies = ARRAY_SIZE(x1e_supplies), .clk_names = (const char **)x1e_clks, .num_clk = ARRAY_SIZE(x1e_clks), + .timer_clk_name = "timer", + .opp_clk_name = "core", .genpds = x1e_genpds, .num_genpds = ARRAY_SIZE(x1e_genpds), }; diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c index 269232499fca..3de25728ed28 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c @@ -397,7 +397,7 @@ static int phy_qcom_mipi_csi2_probe(struct platform_device *pdev) if (!csi2phy->clks[i].id) return dev_err_probe(dev, -EINVAL, "Missing clock-names\n"); - if (!strcmp(csi2phy->clks[i].id, "timer")) { + if (!strcmp(csi2phy->clks[i].id, csi2phy->soc_cfg->timer_clk_name)) { csi2phy->timer_clk = csi2phy->clks[i].clk; break; } @@ -405,7 +405,7 @@ static int phy_qcom_mipi_csi2_probe(struct platform_device *pdev) if (!csi2phy->timer_clk) return dev_err_probe(dev, -ENODEV, "no timer clock\n"); - ret = devm_pm_opp_set_clkname(dev, "core"); + ret = devm_pm_opp_set_clkname(dev, csi2phy->soc_cfg->opp_clk_name); if (ret) return dev_err_probe(dev, ret, "Failed to set opp clkname\n"); diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h index 7e55ae007370..359b58660db8 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h @@ -68,6 +68,9 @@ struct mipi_csi2phy_soc_cfg { const char ** const clk_names; const unsigned int num_clk; + const char * const timer_clk_name; + const char * const opp_clk_name; + const struct mipi_csi2_genpd *genpds; const unsigned int num_genpds; }; -- 2.34.1