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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b245c1c272sm1537440c88.8.2026.11.03.13.41.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 13:41:11 -0800 (PST) From: Anusha Arun Nandi To: Bryan O'Donoghue Cc: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , gjorgji.rosikopulos@oss.qualcomm.com, hariram.purushothaman@oss.qualcomm.com, akapatra@quicinc.com, jigarkumar.zala@oss.qualcomm.com, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/5] phy: qcom-mipi-csi2: Add sc7280 D-PHY provider Date: Tue, 3 Nov 2026 13:41:05 -0800 Message-Id: <20261103214105.3605181-6-anusha.nandi@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261103214105.3605181-1-anusha.nandi@oss.qualcomm.com> References: <20261103214105.3605181-1-anusha.nandi@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMTAzMDA4NiBTYWx0ZWRfX6dDTvsrIaQ2k srEmhql/8P1yyKVoY+W+dfY2Tn68AemP6xeFd0m8rR88NMc2v4YaeN/AF01Vdz35YSiEdf17ONN N7JDUL6WvdRfVbv0kjckBWgQrMZtIGM= X-Authority-Analysis: v=2.4 cv=JeUpPkKV c=1 sm=1 tr=0 ts=6aea54fa cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=NbtrdQoedUgDOuZm1b4A:9 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-GUID: _l4t4Aw8NKP3kH3bU1ttfw45CgG-XyHl X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTAzMDA4NiBTYWx0ZWRfXwB+FdQPQRh4T n/MxgZibgTM4jtIQ02iJHbmE+8bl5imBPXMDterz8LK3zotVJpSbwVQcelAbbNoH0wrCQveqVLa EXcBmjpP0lx9N5eA8ogTPU+JmP0oZopAOENhSfIqHwpdGNkjUH7MIv+vC7VllagUnZdeTYYWaCc YbNJWnuMqP3cZ7I50qymUn3zHYL+kGPVj0rE2+LysIJTh+kld/YYlLGrT5i5jmJEJ4H4k+oxvBF DaFl14gG2qlijfXfnD8JMWm/UZzd8X0CzUUVaR5Hi3oJfubh8noWihOsRn//eyYyaEHB1E9fUvM bExQBkpu977M9au5atVvVcCEgGDZv93ZIAoQeeriZFWaccWqLITgxIzvbk7mzISbN8pztMRAXTB hUW7krkIssIfvGQ2LN3qWngAEPW1U4MQxuSHpGlbGJs935E1WZ31gN/yFdKS0IW4faVVIfGsLWY XrlpjgVnY7DKFlqDg1w== X-Proofpoint-ORIG-GUID: _l4t4Aw8NKP3kH3bU1ttfw45CgG-XyHl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-03_05,2026-11-03_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611030086 Add the SC7280 CSIPHY to the generic MIPI CSI2 PHY driver, bound to a new "qcom,sc7280-csi2-phy" compatible and reusing the existing D-PHY 2-phase hw ops (phy_qcom_mipi_csi2_ops_3ph_1_0). The lane_regs_sc7280[] init sequence is the CSIPHY 5nm 2-phase 2.5Gbps 4-lane D-PHY register set ported from the legacy in-tree camss-csiphy-3ph-1-0.c table, with the entries that table left as do-not-program placeholders simply omitted here rather than carried as a new marker. The soc_cfg declares the core/timer clocks (matching x1e80100's and sa8775p's clock-names convention for this pair) and the vdda-phy/vdda-pll supplies. Like x1e80100 and SA8775P, SC7280's CSIPHY core clock is OPP-scaled against the sensor's link frequency via the shared csiphy_opp_table in kodiak.dtsi, so opp_clk_name is set to "core" here too. SC7280's CSIPHY has a single power-domain, the Titan Top GDSC, matching camss.c's sc7280_resources.pd_name = "top" and kodiak.dtsi's existing camss node; it is not OPP-scaled, only kept enabled. Reviewed-by: Jigarkumar Zala Signed-off-by: Anusha Arun Nandi --- .../qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 122 ++++++++++++++++++ .../phy/qualcomm/phy-qcom-mipi-csi2-core.c | 1 + drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 1 + 3 files changed, 124 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c index 3e93e0b49106..dc31c5cd1475 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c @@ -493,3 +493,125 @@ const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_sa8775p = { .genpds = sa8775p_genpds, .num_genpds = ARRAY_SIZE(sa8775p_genpds), }; + +/* sc7280 5nm 2PH 2p5Gbps 4 lane DPHY mode */ +static const struct mipi_csi2phy_lane_regs lane_regs_sc7280[] = { + {.reg_addr = 0x0030, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0900, .reg_data = 0x05, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0908, .reg_data = 0x10, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0904, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0904, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0004, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x002C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0034, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0010, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x001C, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x003C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0008, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {.reg_addr = 0x0000, .reg_data = 0x8D, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0038, .reg_data = 0xFE, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0014, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0800, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0884, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0730, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C80, .reg_data = 0x05, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C88, .reg_data = 0x10, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C84, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C84, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0704, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x072C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0734, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0710, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x071C, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x073C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0708, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {.reg_addr = 0x0700, .reg_data = 0x80, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x070c, .reg_data = 0xA5, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0738, .reg_data = 0x1F, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0714, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0728, .reg_data = 0x04, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0800, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0884, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0230, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0A00, .reg_data = 0x05, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0A08, .reg_data = 0x10, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0A04, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0A04, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0204, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x022C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0234, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0210, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x021C, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x023C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0208, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {.reg_addr = 0x0200, .reg_data = 0x8D, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0238, .reg_data = 0xFE, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0214, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0800, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0884, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0430, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0B00, .reg_data = 0x05, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0B08, .reg_data = 0x10, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0B04, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0B04, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0404, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x042C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0434, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0410, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x041C, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x043C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0408, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {.reg_addr = 0x0400, .reg_data = 0x8D, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0438, .reg_data = 0xFE, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0414, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0800, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0884, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0630, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C00, .reg_data = 0x05, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C08, .reg_data = 0x10, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C04, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C04, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0604, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x062C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0634, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0610, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x061C, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x063C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0608, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {.reg_addr = 0x0600, .reg_data = 0x8D, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0638, .reg_data = 0xFE, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0614, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0800, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0884, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, +}; + +static const char * const sc7280_clks[] = { + "core", + "timer", +}; + +static const char * const sc7280_supplies[] = { + "vdda-phy", + "vdda-pll", +}; + +static const struct mipi_csi2_genpd sc7280_genpds[] = { + { .name = "top", .scaled = false }, +}; + +const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_sc7280 = { + .ops = &phy_qcom_mipi_csi2_ops_3ph_1_0, + .reg_info = { + .init_seq = lane_regs_sc7280, + .lane_array_size = ARRAY_SIZE(lane_regs_sc7280), + .common_regs_offset = 0x800, + }, + .supply_names = (const char **)sc7280_supplies, + .num_supplies = ARRAY_SIZE(sc7280_supplies), + .clk_names = (const char **)sc7280_clks, + .num_clk = ARRAY_SIZE(sc7280_clks), + .timer_clk_name = "timer", + .opp_clk_name = "core", + .genpds = sc7280_genpds, + .num_genpds = ARRAY_SIZE(sc7280_genpds), +}; diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c index 244e851ff24d..26ee5d9fa4c9 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c @@ -455,6 +455,7 @@ static int phy_qcom_mipi_csi2_probe(struct platform_device *pdev) static const struct of_device_id phy_qcom_mipi_csi2_of_match_table[] = { { .compatible = "qcom,sa8775p-csi2-phy", .data = &mipi_csi2_dphy_sa8775p }, + { .compatible = "qcom,sc7280-csi2-phy", .data = &mipi_csi2_dphy_sc7280 }, { .compatible = "qcom,x1e80100-csi2-phy", .data = &mipi_csi2_dphy_4nm_x1e }, { } }; diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h index 5578741c0930..e2a346bcec89 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h @@ -97,5 +97,6 @@ struct mipi_csi2phy_device { extern const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e; extern const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_sa8775p; +extern const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_sc7280; #endif /* __PHY_QCOM_MIPI_CSI2_H__ */ -- 2.34.1