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[93.34.90.148]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-48fec9cd43bsm328556f8f.14.2026.11.03.14.14.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 14:14:53 -0800 (PST) From: Christian Marangi To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Christian Marangi , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , Joris Vaisvila , Ahmed Naseef , linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next v4 3/6] net: phy: mediatek: generalize cal_cycle function for GE SoC Date: Tue, 3 Nov 2026 23:14:34 +0100 Message-ID: <20261103221439.30502-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261103221439.30502-1-ansuelsmth@gmail.com> References: <20261103221439.30502-1-ansuelsmth@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit In preparation for support of special Software Calibration for Airoha PHY, it's needed to generalize the cal_cycle function as Airoha needs only part of its logic (the wait logic) to complete a calibration cycle. Signed-off-by: Christian Marangi --- drivers/net/phy/mediatek/mtk-ge-soc.c | 32 ++++++++++++++++++--------- drivers/net/phy/mediatek/mtk-ge-soc.h | 3 +++ 2 files changed, 24 insertions(+), 11 deletions(-) diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.c b/drivers/net/phy/mediatek/mtk-ge-soc.c index 2b1e9923db98..f3ce6e67eb38 100644 --- a/drivers/net/phy/mediatek/mtk-ge-soc.c +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c @@ -39,20 +39,11 @@ struct mtk_socphy_shared { struct mtk_socphy_priv priv[4]; }; -/* One calibration cycle consists of: - * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high - * until AD_CAL_COMP is ready to output calibration result. - * 2.Wait until DA_CAL_CLK is available. - * 3.Fetch AD_CAL_COMP_OUT. - */ -static int cal_cycle(struct phy_device *phydev, int devad, - u32 regnum, u16 mask, u16 cal_val) +int mtk_cal_cycle_wait(struct phy_device *phydev) { int reg_val; int ret; - phy_modify_mmd(phydev, devad, regnum, - mask, cal_val); phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, MTK_PHY_DA_CALIN_FLAG); @@ -71,7 +62,26 @@ static int cal_cycle(struct phy_device *phydev, int devad, ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP); if (ret < 0) return ret; - ret = FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret); + + return FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret); +} +EXPORT_SYMBOL_GPL(mtk_cal_cycle_wait); + +/* One calibration cycle consists of: + * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high + * until AD_CAL_COMP is ready to output calibration result. + * 2.Wait until DA_CAL_CLK is available. + * 3.Fetch AD_CAL_COMP_OUT. + */ +static int cal_cycle(struct phy_device *phydev, int devad, + u32 regnum, u16 mask, u16 cal_val) +{ + int ret; + + phy_modify_mmd(phydev, devad, regnum, + mask, cal_val); + + ret = mtk_cal_cycle_wait(phydev); phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); return ret; diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.h b/drivers/net/phy/mediatek/mtk-ge-soc.h index 008efd148a2c..14370b5ce482 100644 --- a/drivers/net/phy/mediatek/mtk-ge-soc.h +++ b/drivers/net/phy/mediatek/mtk-ge-soc.h @@ -354,4 +354,7 @@ enum CAL_MODE { SW_M }; +/* MTK GE SoC common functions */ +int mtk_cal_cycle_wait(struct phy_device *phydev); + #endif /* _MTK_GE_SOC_H_ */ -- 2.55.0