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Wed, 04 Nov 2026 10:49:24 -0800 (PST) Received: from localhost ([2600:1702:7a90:6f9f:66f3:d5d6:2d12:d460]) by smtp.gmail.com with ESMTPSA id 00721157ae682-8b3098c313esm24659757b3.15.2026.11.04.10.49.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2026 10:49:23 -0800 (PST) From: Matt Turner Date: Wed, 04 Nov 2026 13:49:15 -0500 Subject: [PATCH v6 08/13] alpha/perf: optionally randomize the ProfileMe sampling interval X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261104-alpha-profileme-v6-8-63362e9290a3@gmail.com> References: <20261104-alpha-profileme-v6-0-63362e9290a3@gmail.com> In-Reply-To: <20261104-alpha-profileme-v6-0-63362e9290a3@gmail.com> To: Richard Henderson , Magnus Lindholm , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark Cc: linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Matt Turner X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4553; i=mattst88@gmail.com; h=from:subject:message-id; bh=hYabNeE9UaniE1qqxPyCXnHv93dIZeS95X4LQtRwjn8=; b=owGbwMvMwCW25rVmCc8sv+mMp9WSGLJe16nKXd+h18h46nj/1efiPM25mSemye/9tu7MU6tGD 4F3Zby1HR9ZGMS4GGaKKbLErVdkmdW2Y6nPaelfMHNYmUCGSIs0MAABCwNfbmJeqZGOkZ6ptqGe IZChYxQPkdNj0MgsLi5NLdJNKyhyyMsvSSzJzM8r1ssvSM0rSC/QS8tMK8nIyC8qTgUaoZeXWmL q6uhmZGhgYuloYeZk4Whq4uzsZOjk5ujo7OpkZGluYuBs6WjiamnOwMUpAHONewzD/1Dnb7VtZ1 ftvi77/urcrpWzva9m1kYw3P76PGrvwgkPNLwZGX44rnJPnpHw99RqGaFplz9IpJWpvCqL/fOOQ /2KqHz7ZmYA X-Developer-Key: i=mattst88@gmail.com; a=openpgp; fpr=3BB639E56F861FA2E86505690FDD682D974CA72A A fixed sampling interval can phase-lock with a loop whose length divides it, so that the same few instructions are profiled over and over while the rest of the loop is never seen. DCPI avoided this by randomizing the interval. Add a randomize config bit that varies each interval by up to 1/16 of the period in either direction. Only ProfileMe events accept it, since Aggregate mode samples already land a variable distance from the instruction that overflowed. Counts are unaffected, because prev_count already records the value written to the counter. The jitter is computed with mul_u64_u32_shr() and the sum saturates, so that a period beyond 32 bits cannot overflow. The jitter comes from a per-CPU prandom state rather than get_random_u32_below(), which takes the batched entropy local lock and triggers an invalid wait context report from lockdep in the PMI. Signed-off-by: Matt Turner Reviewed-by: Magnus Lindholm Tested-by: Magnus Lindholm --- arch/alpha/kernel/perf_event.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c index f6546d648133..b33677cc23ca 100644 --- a/arch/alpha/kernel/perf_event.c +++ b/arch/alpha/kernel/perf_event.c @@ -16,6 +16,9 @@ #include #include #include +#include +#include +#include #include #include @@ -34,10 +37,12 @@ /* Layout of attr.config for PERF_TYPE_RAW events; see format/ in sysfs. */ #define ALPHA_PERF_CONFIG_EVENT 0xffULL #define ALPHA_PERF_CONFIG_PROFILEME BIT_ULL(8) +#define ALPHA_PERF_CONFIG_RANDOMIZE BIT_ULL(9) /* hw_perf_event.flags */ #define ALPHA_PERF_FLAG_WRAPPED 0x1 #define ALPHA_PERF_FLAG_PROFILEME 0x2 +#define ALPHA_PERF_FLAG_RANDOMIZE 0x4 /* For tracking PMCs and the hw events they monitor on each CPU. */ struct cpu_hw_events { @@ -61,6 +66,9 @@ struct cpu_hw_events { }; DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); +/* For randomizing sample intervals from the PMI, where locks are not allowed. */ +static DEFINE_PER_CPU(struct rnd_state, alpha_perf_rnd); + /* @@ -248,10 +256,12 @@ static int ev67_raw_event_valid(u64 config) PMU_FORMAT_ATTR(event, "config:0-7"); PMU_FORMAT_ATTR(profileme, "config:8"); +PMU_FORMAT_ATTR(randomize, "config:9"); static struct attribute *ev67_format_attrs[] = { &format_attr_event.attr, &format_attr_profileme.attr, + &format_attr_randomize.attr, NULL, }; @@ -389,6 +399,22 @@ static int alpha_perf_event_set_period(struct perf_event *event, ret = 1; } + /* + * Vary each new interval by up to 1/16 of the period either way, so + * the samples cannot phase-lock with a loop whose length divides the + * period. The count stays exact because prev_count records the value + * written. + */ + if (ret && (hwc->flags & ALPHA_PERF_FLAG_RANDOMIZE) && period >= 8) { + long jitter = period / 8; + u32 r = prandom_u32_state(this_cpu_ptr(&alpha_perf_rnd)); + long offset = mul_u64_u32_shr(jitter, r, 32) - jitter / 2; + + if (check_add_overflow(left, offset, &left)) + left = LONG_MAX; + local64_set(&hwc->period_left, left); + } + /* * Hardware restrictions require that the counters must not be * written with values that are too close to the maximum period. @@ -763,7 +789,8 @@ static int __hw_perf_event_init(struct perf_event *event) return -EOPNOTSUPP; } else if (attr->type == PERF_TYPE_RAW) { if (attr->config & ~(ALPHA_PERF_CONFIG_EVENT | - ALPHA_PERF_CONFIG_PROFILEME)) + ALPHA_PERF_CONFIG_PROFILEME | + ALPHA_PERF_CONFIG_RANDOMIZE)) return -EINVAL; ev = attr->config & ALPHA_PERF_CONFIG_EVENT; if (!alpha_pmu->raw_event_valid(ev)) @@ -791,6 +818,14 @@ static int __hw_perf_event_init(struct perf_event *event) return -EINVAL; hwc->flags = profileme ? ALPHA_PERF_FLAG_PROFILEME : 0; + if (attr->type == PERF_TYPE_RAW && + (attr->config & ALPHA_PERF_CONFIG_RANDOMIZE)) { + if (!profileme) + return -EINVAL; + prandom_init_once(&alpha_perf_rnd); + hwc->flags |= ALPHA_PERF_FLAG_RANDOMIZE; + } + /* * We place the event type in event_base here and leave calculation * of the codes to programme the PMU for alpha_pmu_enable() because -- 2.55.0