[PATCH 0/2] gpio: aspeed: Fix lost interrupts from write-1-to-clear status bits

[Billy Tsai <billy_tsai@aspeedtech.com>]

The Aspeed GPIO interrupt status bits are write-1-to-clear on every
generation, but the driver updates them with read-modify-write helpers
that write a pending status bit back as 1. Each write therefore clears
interrupts that have not been handled yet.

Patch 1 fixes G4 (AST2400/AST2500/AST2600), where the status register
covers a 32-line bank. Acking one line clears every interrupt pending
in the bank, and an edge that latches after the handler has read the
status register is lost. This was observed on an AST2600 BMC with two
lines of the same bank toggling together at host power-off.

Patch 2 fixes G7 (AST2700), where each line's status bit sits in that
line's own control register. Updating any other field of the register
while the line's interrupt is pending clears it.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
Billy Tsai (2):
      gpio: aspeed: Clear only the acked line's G4 interrupt status
      gpio: aspeed: Preserve the pending G7 interrupt status on control writes

 drivers/gpio/gpio-aspeed.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)
---
base-commit: 65ba8f34ec886ec72b2c07ddc8cf3d815c32869d
change-id: 20261104-gpio-aspeed-irq-status-1fc21a4edfcf

Best regards,
-- 
Billy Tsai <billy_tsai@aspeedtech.com>