From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793814505; b=zoES8Ue1ZKL8K+vh+l8OqJpPRmlUKSLFMIdH/nGvednxpwrI4hm5toxSYXYaVt+kYsbV FKJXVSrO4TqLgi4sDkulpXg+/FO5wDAEejX5pCKgN/LJvOmWc45LN6WVuxQ6zklFalxrL 0yyBDhDyp0tow7UgVnBkCJNaCC/9W2fbJ81xos+Iis6vlDvl77xlJwnMz4sCxOY903NGc g6HVV2+V81OjoKSCDlA2cbZ7PdPtnTFK6j8G2aTxeQtfRdffT08wgeOioj2NvTKRLt5On Ja+SilqPYzbLtGVwFbV7jNPfLR9bh2e7bPpVDspTvB6vDdDLBtq27jYAPDbkSg0vzxw== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793814505; h=DMARC-Filter:Received:Received:DKIM-Signature:From:Date:Subject: MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id: References:In-Reply-To:To:Cc:X-Mailer; bh=kk4wiL5SliP/Vyu3xQ313k+8HyFDPUBhSH/Hd019iao=; b=pOUU0S2ZZhEKnVTLUIMiKECKhMO4CD6gR0/N5b406+QjUXIXWbOe/R7MYo3QsTrwaef7 6M8pYLcS3WJ2yxKjaRAAsjOVgl6KIh6B+7BbYxbXinQ6hBwJxlEVGnB30MmBPdQ7zPPBv OWVSwJ0kLT9mQfmJKeANY8mmONBYzU+eiFNnp7fXobNW9L1xBqcGqX10y7wXzVBWPZu5p yg0lIKBGHzhDqjgqjtL0C+UJkNpc2mXV3rv+NVQ9WRAe2AEkvZ1KUtL6xDyUy2pZbUcVR OGNl61L6Rz+i36d6weCMOiy821ZHqrI1nvBM477etBuYfuVyKTDw+ULhQ2+Wo1Lpmkg== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=foss header.b=HAx+Cohv; arc=none smtp.remote-ip=217.140.110.172 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BDA92606D816 for ; Wed, 4 Nov 2026 17:48:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org BDA92606D816 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key, unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=foss header.b=HAx+Cohv Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 186EE1BB2; Wed, 4 Nov 2026 09:48:21 -0800 (PST) Received: from e133894.arm.com (e133894.arm.com [10.2.80.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D586C3F673; Wed, 4 Nov 2026 09:48:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1793814504; bh=tOhPiHRXnPNTsYhv9r+JKx25HW1yCfJsmlAkFpXs/Z4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=HAx+CohvVB5xvosrrOgpAoaFO3yhZIfak0ljQOWbcfhqqODDJpCGbWIT8FBkeM78t /xoxFjSoZGji5N8bTNp8GwK+CyzpyH83OYm3h/ENfHFRh5+enuBnM6XcNvcGaBAq5E 9ZuPOUfe/CjIcsftFnNFnIIhAq8w5QO0Pn9lqdfw= From: Sascha Bischoff Date: Wed, 04 Nov 2026 17:47:56 +0000 Subject: [PATCH v2 02/10] irqchip/gic-v5: Only set IRS DPS when 1ofN routing is supported X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261104-host_gicv5_fixes-v2-2-e47ad20ea3c8@arm.com> References: <20261104-host_gicv5_fixes-v2-0-e47ad20ea3c8@arm.com> In-Reply-To: <20261104-host_gicv5_fixes-v2-0-e47ad20ea3c8@arm.com> To: Marc Zyngier , Lorenzo Pieralisi , Thomas Gleixner , Radu Rendec , Timothy Hayes , Catalin Marinas , Jonathan Cameron , "Rafael J. Wysocki" Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sascha Bischoff X-Mailer: b4 0.15.2 IRS_PE_CR0.DPS is RES0 when the IRS does not support 1ofN routing. Read the capability from IRS_IDR0 and skip programming DPS on systems without support for 1ofN routing, rather than blindly writing it. Fixes: 5cb1b6dab2def ("irqchip/gic-v5: Add GICv5 IRS/SPI support") Acked-by: Lorenzo Pieralisi Signed-off-by: Sascha Bischoff --- drivers/irqchip/irq-gic-v5-irs.c | 14 +++++++++----- include/linux/irqchip/arm-gic-v5.h | 1 + 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-gic-v5-irs.c b/drivers/irqchip/irq-gic-v5-irs.c index 9d60f474aa4f6..4edf787f3f97f 100644 --- a/drivers/irqchip/irq-gic-v5-irs.c +++ b/drivers/irqchip/irq-gic-v5-irs.c @@ -541,12 +541,15 @@ int gicv5_irs_register_cpu(int cpuid) return -ENXIO; } - cr0 = FIELD_PREP(GICV5_IRS_PE_CR0_DPS, 0x1); - irs_writel_relaxed(irs_data, cr0, GICV5_IRS_PE_CR0); + /* IRS_PE_CR0.DPS is RES0 when 1ofN routing is unsupported. */ + if (gicv5_global_data.one_of_n) { + cr0 = FIELD_PREP(GICV5_IRS_PE_CR0_DPS, 0x1); + irs_writel_relaxed(irs_data, cr0, GICV5_IRS_PE_CR0); - ret = gicv5_irs_wait_for_pe_cr0(irs_data); - if (ret) - return ret; + ret = gicv5_irs_wait_for_pe_cr0(irs_data); + if (ret) + return ret; + } pr_debug("CPU %d enabled PE IAFFID 0x%x\n", cpuid, iaffid); @@ -725,6 +728,7 @@ static int __init gicv5_irs_init(struct gicv5_irs_chip_data *irs_data) if (list_empty(&irs_nodes)) { idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR0); gicv5_global_data.virt_capable = !!FIELD_GET(GICV5_IRS_IDR0_VIRT, idr); + gicv5_global_data.one_of_n = !!FIELD_GET(GICV5_IRS_IDR0_ONE_N, idr); idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR1); irs_setup_pri_bits(idr); diff --git a/include/linux/irqchip/arm-gic-v5.h b/include/linux/irqchip/arm-gic-v5.h index 299e75bc95255..34e22e7d4a4c7 100644 --- a/include/linux/irqchip/arm-gic-v5.h +++ b/include/linux/irqchip/arm-gic-v5.h @@ -532,6 +532,7 @@ struct gicv5_chip_data { u8 cpuif_id_bits; u8 irs_pri_bits; bool virt_capable; + bool one_of_n; struct { __le64 *l1ist_addr; u32 l2_size; -- 2.34.1