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Wed, 04 Nov 2026 10:54:08 -0800 (PST) Received: from localhost ([2600:1702:7a90:6f9f:66f3:d5d6:2d12:d460]) by smtp.gmail.com with ESMTPSA id 00721157ae682-8b309b9f50csm24367767b3.38.2026.11.04.10.54.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2026 10:54:07 -0800 (PST) From: Matt Turner Date: Wed, 04 Nov 2026 13:53:58 -0500 Subject: [PATCH v4 3/3] perf alpha: Add perf mem support X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261104-perf-alpha-profileme-v4-3-1771ea02950e@gmail.com> References: <20261104-perf-alpha-profileme-v4-0-1771ea02950e@gmail.com> In-Reply-To: <20261104-perf-alpha-profileme-v4-0-1771ea02950e@gmail.com> To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark Cc: Magnus Lindholm , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Matt Turner X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3965; i=mattst88@gmail.com; h=from:subject:message-id; bh=0IeeS9SsfB54T5WtkW3dlFw63jBXywse/saigUal3p0=; b=owGbwMvMwCW25rVmCc8sv+mMp9WSGLJe17sI+KTmH2NK6FLpMLM9q9LsdfxenIdd/6flNZzVl if50+M7PrIwiHExzBRTZIlbr8gyq23HUp/T0r9g5rAygQyRFmlgAAIWBr7cxLxSIx0jPVNtQz1D IEPHKB4ip8egkVlcXJpapJtWUOSQl1+SWJKZn1esl1+QmleQXqCXlplWkpGRX1ScCjRCLy+1xNT V0c3I0MDE0tHCzMnC0dTE2dnJ0MnN0dHZ1cnI0tzEwNnS0cTV0pyBi1MA5pofqQz/c1geBdp8vX yjJ6XVfMe+23zubQve5zYnrzyl927NxiM8jAz/C6fyLrxZrL1aK3Tzg4k5u6+9/VwcdGRldrDLQ hatRRJ1TAA= X-Developer-Key: i=mattst88@gmail.com; a=openpgp; fpr=3BB639E56F861FA2E86505690FDD682D974CA72A The Alpha kernel series "alpha/perf: add ProfileMe sampling" reports the data source of ProfileMe samples of loads and stores: whether they hit or missed the DTB, and whether they were loads, stores or prefetches. Give the Alpha core PMU a mem-ldst event, cpu/cycles,profileme/, as AMD does with IBS Op. cycles:p is not used, as precise events sample only retired instructions, and a load or store that misses the DTB is aborted and refetched. The profileme format bit only exists on the EV67 and later, which have ProfileMe. Suggested-by: Ian Rogers Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Matt Turner --- tools/perf/Documentation/perf-mem.txt | 3 +++ tools/perf/arch/alpha/Build | 2 +- tools/perf/arch/alpha/util/Build | 2 ++ tools/perf/arch/alpha/util/mem-events.c | 17 +++++++++++++++++ tools/perf/arch/alpha/util/mem-events.h | 7 +++++++ tools/perf/arch/alpha/util/pmu.c | 11 +++++++++++ 6 files changed, 41 insertions(+), 1 deletion(-) diff --git a/tools/perf/Documentation/perf-mem.txt b/tools/perf/Documentation/perf-mem.txt index fe51c5e3333d..cb439940ce90 100644 --- a/tools/perf/Documentation/perf-mem.txt +++ b/tools/perf/Documentation/perf-mem.txt @@ -34,6 +34,9 @@ be sampled. On AMD this use IBS Op PMU to sample load-store operations. +On Alpha this uses ProfileMe, on the EV67 and later, to sample all +instructions. Loads and stores report whether they hit or missed the DTB. + COMMON OPTIONS -------------- -f:: diff --git a/tools/perf/arch/alpha/Build b/tools/perf/arch/alpha/Build index 1bb8bf6d7fd4..e63eabc2c8f4 100644 --- a/tools/perf/arch/alpha/Build +++ b/tools/perf/arch/alpha/Build @@ -1 +1 @@ -# empty +perf-util-y += util/ diff --git a/tools/perf/arch/alpha/util/Build b/tools/perf/arch/alpha/util/Build new file mode 100644 index 000000000000..8d924b229470 --- /dev/null +++ b/tools/perf/arch/alpha/util/Build @@ -0,0 +1,2 @@ +perf-util-y += mem-events.o +perf-util-y += pmu.o diff --git a/tools/perf/arch/alpha/util/mem-events.c b/tools/perf/arch/alpha/util/mem-events.c new file mode 100644 index 000000000000..d3cbca1993b4 --- /dev/null +++ b/tools/perf/arch/alpha/util/mem-events.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "util/map_symbol.h" +#include "util/mem-events.h" +#include "mem-events.h" + +#define E(t, n, s, l, a) { .tag = t, .name = n, .event_name = s, .ldlat = l, .aux_event = a } + +/* + * ProfileMe samples loads and stores alike, and reports DTB hits and misses + * in the data source. A precise event would sample only retired + * instructions, which leaves out the DTB misses, so set the profileme bit. + */ +struct perf_mem_event perf_mem_events_alpha[PERF_MEM_EVENTS__MAX] = { + E(NULL, NULL, NULL, false, 0), + E(NULL, NULL, NULL, false, 0), + E("mem-ldst", "%s/cycles,profileme/", "cycles", false, 0), +}; diff --git a/tools/perf/arch/alpha/util/mem-events.h b/tools/perf/arch/alpha/util/mem-events.h new file mode 100644 index 000000000000..311448cf1218 --- /dev/null +++ b/tools/perf/arch/alpha/util/mem-events.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ALPHA_MEM_EVENTS_H +#define _ALPHA_MEM_EVENTS_H + +extern struct perf_mem_event perf_mem_events_alpha[PERF_MEM_EVENTS__MAX]; + +#endif /* _ALPHA_MEM_EVENTS_H */ diff --git a/tools/perf/arch/alpha/util/pmu.c b/tools/perf/arch/alpha/util/pmu.c new file mode 100644 index 000000000000..d19dfc979b08 --- /dev/null +++ b/tools/perf/arch/alpha/util/pmu.c @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "../../../util/pmu.h" +#include "mem-events.h" + +void perf_pmu__arch_init(struct perf_pmu *pmu) +{ + /* ProfileMe is only on the EV67 and later. */ + if (pmu->is_core && perf_pmu__has_format(pmu, "profileme")) + pmu->mem_events = perf_mem_events_alpha; +} -- 2.55.0